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d1ba364627
Add basic ACPI table information needed to understand the CXL driver probe process. Signed-off-by: Gregory Price <gourry@gourry.net> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://patch.msgid.link/20250512162134.3596150-6-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com>
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1.2 KiB
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33 lines
1.2 KiB
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.. SPDX-License-Identifier: GPL-2.0
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===========================================
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HMAT - Heterogeneous Memory Attribute Table
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===========================================
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The Heterogeneous Memory Attributes Table contains information such as cache
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attributes and bandwidth and latency details for memory proximity domains.
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For the purpose of this document, we will only discuss the SSLIB entry.
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SLLBI
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=====
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The System Locality Latency and Bandwidth Information records latency and
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bandwidth information for proximity domains.
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This table is used by Linux to configure interleave weights and memory tiers.
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Example (Heavily truncated for brevity) ::
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Structure Type : 0001 [SLLBI]
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Data Type : 00 <- Latency
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Target Proximity Domain List : 00000000
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Target Proximity Domain List : 00000001
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Entry : 0080 <- DRAM LTC
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Entry : 0100 <- CXL LTC
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Structure Type : 0001 [SLLBI]
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Data Type : 03 <- Bandwidth
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Target Proximity Domain List : 00000000
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Target Proximity Domain List : 00000001
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Entry : 1200 <- DRAM BW
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Entry : 0200 <- CXL BW
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