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89e6684538
ifc can connect nor, nand and fpag. Split "^.*@..." into "nand@..." and "(flash|fpga|board-control|cpld)@..." to better describe the child's node binding requirements. Fix below warning: arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dtb: /soc/memory-controller@1530000/nand@1,0: failed to match any schema with compatible: ['fsl,ifc-nand'] Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20240909165358.2384975-1-Frank.Li@nxp.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
136 lines
3.5 KiB
YAML
136 lines
3.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,ifc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: FSL/NXP Integrated Flash Controller
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maintainers:
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- Shawn Guo <shawnguo@kernel.org>
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description: |
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NXP's integrated flash controller (IFC) is an advanced version of the
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enhanced local bus controller which includes similar programming and signal
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interfaces with an extended feature set. The IFC provides access to multiple
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external memory types, such as NAND flash (SLC and MLC), NOR flash, EPROM,
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SRAM and other memories where address and data are shared on a bus.
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properties:
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$nodename:
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pattern: "^memory-controller@[0-9a-f]+$"
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compatible:
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const: fsl,ifc
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"#address-cells":
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enum: [2, 3]
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description: |
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Should be either two or three. The first cell is the chipselect
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number, and the remaining cells are the offset into the chipselect.
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"#size-cells":
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enum: [1, 2]
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description: |
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Either one or two, depending on how large each chipselect can be.
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reg:
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maxItems: 1
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interrupts:
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minItems: 1
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maxItems: 2
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description: |
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IFC may have one or two interrupts. If two interrupt specifiers are
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present, the first is the "common" interrupt (CM_EVTER_STAT), and the
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second is the NAND interrupt (NAND_EVTER_STAT). If there is only one,
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that interrupt reports both types of event.
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little-endian:
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type: boolean
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description: |
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If this property is absent, the big-endian mode will be in use as default
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for registers.
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ranges:
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description: |
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Each range corresponds to a single chipselect, and covers the entire
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access window as configured.
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patternProperties:
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"^nand@[a-f0-9]+(,[a-f0-9]+)+$":
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type: object
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properties:
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compatible:
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const: fsl,ifc-nand
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reg:
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maxItems: 1
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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patternProperties:
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"^partition@[0-9a-f]+":
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$ref: /schemas/mtd/partitions/partition.yaml#
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deprecated: true
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required:
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- compatible
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- reg
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additionalProperties: false
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"(flash|fpga|board-control|cpld)@[a-f0-9]+(,[a-f0-9]+)+$":
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type: object
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oneOf:
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- $ref: /schemas/board/fsl,fpga-qixis.yaml#
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- $ref: /schemas/mtd/mtd-physmap.yaml#
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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- interrupts
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additionalProperties: false
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examples:
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- |
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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memory-controller@ffe1e000 {
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compatible = "fsl,ifc";
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#address-cells = <2>;
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#size-cells = <1>;
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reg = <0x0 0xffe1e000 0 0x2000>;
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interrupts = <16 2 19 2>;
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little-endian;
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/* NOR, NAND Flashes and CPLD on board */
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ranges = <0x0 0x0 0x0 0xee000000 0x02000000>,
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<0x1 0x0 0x0 0xffa00000 0x00010000>,
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<0x3 0x0 0x0 0xffb00000 0x00020000>;
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flash@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x2000000>;
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bank-width = <2>;
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device-width = <1>;
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partition@0 {
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/* 32MB for user data */
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reg = <0x0 0x02000000>;
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label = "NOR Data";
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};
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};
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};
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};
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