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94555704be
Convert the TI Keystone 2 interrupt controller binding to schema format. It's a straight-forward conversion of the typical interrupt controller. Link: https://lore.kernel.org/r/20250505144908.1293785-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
64 lines
1.5 KiB
YAML
64 lines
1.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/ti,keystone-irq.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Keystone 2 IRQ controller IP
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maintainers:
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- Grygorii Strashko <grygorii.strashko@ti.com>
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description:
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On Keystone SOCs, DSP cores can send interrupts to ARM host using the IRQ
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controller IP. It provides 28 IRQ signals to ARM. The IRQ handler running on
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HOST OS can identify DSP signal source by analyzing SRCCx bits in IPCARx
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registers. This is one of the component used by the IPC mechanism used on
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Keystone SOCs.
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properties:
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compatible:
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const: ti,keystone-irq
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reg:
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maxItems: 1
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interrupt-controller: true
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'#interrupt-cells':
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const: 1
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interrupts:
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maxItems: 1
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ti,syscon-dev:
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description: Phandle and offset to syscon device
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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- items:
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- description: Phandle to syscon device control registers
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- description: Offset to control register
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required:
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- compatible
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- reg
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- interrupt-controller
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- '#interrupt-cells'
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- interrupts
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- ti,syscon-dev
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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interrupt-controller@2a0 {
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compatible = "ti,keystone-irq";
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reg = <0x2a0 0x4>;
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ti,syscon-dev = <&devctrl 0x2a0>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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