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d8c56cea72
StarFive SoCs like the JH8100 use a interrupt controller. Add a binding for it. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240226055025.1669223-2-changhuang.liang@starfivetech.com
62 lines
1.3 KiB
YAML
62 lines
1.3 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/starfive,jh8100-intc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive External Interrupt Controller
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description:
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StarFive SoC JH8100 contain a external interrupt controller. It can be used
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to handle high-level input interrupt signals. It also send the output
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interrupt signal to RISC-V PLIC.
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maintainers:
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- Changhuang Liang <changhuang.liang@starfivetech.com>
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properties:
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compatible:
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const: starfive,jh8100-intc
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reg:
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maxItems: 1
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clocks:
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description: APB clock for the interrupt controller
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maxItems: 1
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resets:
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description: APB reset for the interrupt controller
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maxItems: 1
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interrupts:
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maxItems: 1
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interrupt-controller: true
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"#interrupt-cells":
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- resets
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- interrupts
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- interrupt-controller
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- "#interrupt-cells"
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additionalProperties: false
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examples:
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- |
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interrupt-controller@12260000 {
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compatible = "starfive,jh8100-intc";
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reg = <0x12260000 0x10000>;
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clocks = <&syscrg_ne 76>;
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resets = <&syscrg_ne 13>;
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interrupts = <45>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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