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Convert fsl,vf610-mscm-ir.txt to yaml format. Additional changes: - remove label at example dts. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20250724190342.1321632-1-Frank.Li@nxp.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
64 lines
1.8 KiB
YAML
64 lines
1.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/fsl,vf610-mscm-ir.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale Vybrid Miscellaneous System Control - Interrupt Router
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description:
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The MSCM IP contains multiple sub modules, this binding describes the second
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block of registers which control the interrupt router. The interrupt router
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allows to configure the recipient of each peripheral interrupt. Furthermore
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it controls the directed processor interrupts. The module is available in all
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Vybrid SoC's but is only really useful in dual core configurations (VF6xx
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which comes with a Cortex-A5/Cortex-M4 combination).
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maintainers:
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- Frank Li <Frank.Li@nxp.com>
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properties:
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compatible:
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const: fsl,vf610-mscm-ir
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reg:
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maxItems: 1
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fsl,cpucfg:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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The handle to the MSCM CPU configuration node, required
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to get the current CPU ID
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interrupt-controller: true
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'#interrupt-cells':
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const: 2
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description:
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Two cells, interrupt number and cells.
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The hardware interrupt number according to interrupt
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assignment of the interrupt router is required.
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Flags get passed only when using GIC as parent. Flags
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encoding as documented by the GIC bindings.
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required:
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- compatible
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- reg
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- fsl,cpucfg
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- interrupt-controller
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- '#interrupt-cells'
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additionalProperties: false
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examples:
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- |
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interrupt-controller@40001800 {
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compatible = "fsl,vf610-mscm-ir";
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reg = <0x40001800 0x400>;
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fsl,cpucfg = <&mscm_cpucfg>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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};
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