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Add the DT binding documentation for Andes machine-level software interrupt controller. In the Andes platform such as QiLai SoC, the PLIC module is instantiated a second time with all interrupt sources tied to zero as the software interrupt controller (PLICSW). PLICSW can generate machine-level software interrupts through programming its registers. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Link: https://lore.kernel.org/r/20250711133025.2192404-5-ben717@andestech.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
55 lines
1.5 KiB
YAML
55 lines
1.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/andestech,plicsw.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Andes machine-level software interrupt controller
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description:
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In the Andes platform such as QiLai SoC, the PLIC module is instantiated a
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second time with all interrupt sources tied to zero as the software interrupt
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controller (PLIC_SW). PLIC_SW directly connects to the machine-mode
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inter-processor interrupt lines of CPUs, so RISC-V per-CPU local interrupt
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controller is the parent interrupt controller for PLIC_SW. PLIC_SW can
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generate machine-mode inter-processor interrupts through programming its
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registers.
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maintainers:
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- Ben Zong-You Xie <ben717@andestech.com>
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properties:
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compatible:
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items:
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- enum:
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- andestech,qilai-plicsw
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- const: andestech,plicsw
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reg:
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maxItems: 1
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interrupts-extended:
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minItems: 1
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maxItems: 15872
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description:
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Specifies which harts are connected to the PLIC_SW. Each item must points
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to a riscv,cpu-intc node, which has a riscv cpu node as parent.
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additionalProperties: false
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required:
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- compatible
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- reg
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- interrupts-extended
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examples:
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- |
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interrupt-controller@400000 {
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compatible = "andestech,qilai-plicsw", "andestech,plicsw";
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reg = <0x400000 0x400000>;
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interrupts-extended = <&cpu0intc 3>,
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<&cpu1intc 3>,
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<&cpu2intc 3>,
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<&cpu3intc 3>;
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};
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