linux/Documentation/devicetree/bindings/dma/atmel,at91sam9g45-dma.yaml
Durai Manickam KR a54ec77039 dt-bindings: dma: convert atmel-dma.txt to YAML
Add a description, required properties, appropriate compatibles and
missing properties like clocks and clock-names which are not defined in
the text binding for all the SoCs that are supported by microchip.
Update the text binding name `atmel-dma.txt` to
`atmel,at91sam9g45-dma.yaml` for the files which reference to
`atmel-dma.txt`. Drop Tudor name from maintainers.

Signed-off-by: Durai Manickam KR <durai.manickamkr@microchip.com>
Signed-off-by: Charan Pedumuru <charan.pedumuru@microchip.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250203-test-v4-1-a9ec3eded1c7@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-10 19:11:59 +05:30

69 lines
1.7 KiB
YAML

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/atmel,at91sam9g45-dma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Atmel Direct Memory Access Controller (DMA)
maintainers:
- Ludovic Desroches <ludovic.desroches@microchip.com>
description:
The Atmel Direct Memory Access Controller (DMAC) transfers data from a source
peripheral to a destination peripheral over one or more AMBA buses. One channel
is required for each source/destination pair. In the most basic configuration,
the DMAC has one master interface and one channel. The master interface reads
the data from a source and writes it to a destination. Two AMBA transfers are
required for each DMAC data transfer. This is also known as a dual-access transfer.
The DMAC is programmed via the APB interface.
properties:
compatible:
enum:
- atmel,at91sam9g45-dma
- atmel,at91sam9rl-dma
reg:
maxItems: 1
interrupts:
maxItems: 1
"#dma-cells":
description:
Must be <2>, used to represent the number of integer cells in the dma
property of client devices. The two cells in order are
1. The first cell represents the channel number.
2. The second cell is 0 for RX and 1 for TX transfers.
const: 2
clocks:
maxItems: 1
clock-names:
const: dma_clk
required:
- compatible
- reg
- interrupts
- "#dma-cells"
- clocks
- clock-names
additionalProperties: false
examples:
- |
dma-controller@ffffec00 {
compatible = "atmel,at91sam9g45-dma";
reg = <0xffffec00 0x200>;
interrupts = <21>;
#dma-cells = <2>;
clocks = <&pmc 2 20>;
clock-names = "dma_clk";
};
...