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Document the MDSS and DPU hardware found on the Qualcomm SM6150 platform. Signed-off-by: Li Liu <quic_lliu6@quicinc.com> Signed-off-by: Fange Zhang <quic_fangez@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/628003/ Link: https://lore.kernel.org/r/20241210-add-display-support-for-qcs615-platform-v4-3-2d875a67602d@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
109 lines
2.6 KiB
YAML
109 lines
2.6 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/qcom,sm6150-dpu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SM6150 Display DPU
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maintainers:
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- Abhinav Kumar <quic_abhinavk@quicinc.com>
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- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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$ref: /schemas/display/msm/dpu-common.yaml#
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properties:
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compatible:
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const: qcom,sm6150-dpu
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reg:
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items:
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- description: Address offset and size for mdp register set
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- description: Address offset and size for vbif register set
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reg-names:
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items:
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- const: mdp
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- const: vbif
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clocks:
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items:
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- description: Display ahb clock
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- description: Display hf axi clock
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- description: Display core clock
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- description: Display vsync clock
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clock-names:
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items:
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- const: iface
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- const: bus
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- const: core
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- const: vsync
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/qcom,rpmhpd.h>
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display-controller@ae01000 {
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compatible = "qcom,sm6150-dpu";
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reg = <0x0ae01000 0x8f000>,
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<0x0aeb0000 0x2008>;
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reg-names = "mdp", "vbif";
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clocks = <&dispcc_mdss_ahb_clk>,
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<&gcc_disp_hf_axi_clk>,
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<&dispcc_mdss_mdp_clk>,
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<&dispcc_mdss_vsync_clk>;
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clock-names = "iface", "bus", "core", "vsync";
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assigned-clocks = <&dispcc_mdss_vsync_clk>;
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assigned-clock-rates = <19200000>;
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operating-points-v2 = <&mdp_opp_table>;
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power-domains = <&rpmhpd RPMHPD_CX>;
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interrupt-parent = <&mdss>;
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interrupts = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dpu_intf0_out: endpoint {
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};
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};
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port@1 {
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reg = <1>;
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dpu_intf1_out: endpoint {
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remote-endpoint = <&mdss_dsi0_in>;
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};
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};
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};
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mdp_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-19200000 {
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opp-hz = /bits/ 64 <19200000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-25600000 {
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opp-hz = /bits/ 64 <25600000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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opp-307200000 {
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opp-hz = /bits/ 64 <307200000>;
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required-opps = <&rpmhpd_opp_nom>;
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};
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};
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};
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...
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