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a1ed5860ef
Apart from the already handled data bus (MAS_MDP_Pn<->DDR), there are other connection paths: - a path that connects rotator block to the DDR. - a path that needs to be handled to ensure MDSS register access functions properly, namely the "reg bus", a.k.a the CPU-MDSS CFG interconnect. Describe these paths to allow using them in device trees and in the driver. [Konrad: rework for one vs two MDP paths, update examples] Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/569480/ Link: https://lore.kernel.org/r/20231125-topic-rb1_feat-v3-2-4cbb567743bb@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
107 lines
2.3 KiB
YAML
107 lines
2.3 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/mdss-common.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display MDSS common properties
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maintainers:
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- Krishna Manikandan <quic_mkrishn@quicinc.com>
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- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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- Rob Clark <robdclark@gmail.com>
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description:
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Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
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sub-blocks like DPU display controller, DSI and DP interfaces etc.
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# Do not select this by default, otherwise it is also selected for qcom,mdss
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# devices.
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select:
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false
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properties:
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$nodename:
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pattern: "^display-subsystem@[0-9a-f]+$"
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reg:
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maxItems: 1
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reg-names:
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const: mdss
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power-domains:
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maxItems: 1
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clocks:
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minItems: 2
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maxItems: 4
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clock-names:
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minItems: 2
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maxItems: 4
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interrupts:
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maxItems: 1
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interrupt-controller: true
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"#address-cells": true
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"#size-cells": true
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"#interrupt-cells":
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const: 1
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iommus:
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minItems: 1
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items:
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- description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
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- description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
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ranges: true
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# This is not a perfect description, but it's impossible to discern and match
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# the entries like we do with interconnect-names
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interconnects:
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minItems: 1
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items:
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- description: Interconnect path from mdp0 (or a single mdp) port to the data bus
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- description: Interconnect path from mdp1 port to the data bus
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- description: Interconnect path from CPU to the reg bus
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interconnect-names:
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oneOf:
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- minItems: 1
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items:
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- const: mdp0-mem
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- const: cpu-cfg
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- minItems: 2
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items:
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- const: mdp0-mem
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- const: mdp1-mem
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- const: cpu-cfg
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resets:
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items:
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- description: MDSS_CORE reset
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memory-region:
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maxItems: 1
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description:
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Phandle to a node describing a reserved framebuffer memory region.
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For example, the splash memory region set up by the bootloader.
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required:
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- reg
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- reg-names
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- power-domains
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- clocks
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- interrupts
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- interrupt-controller
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- iommus
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- ranges
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additionalProperties: true
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