mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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34bdf809a5
Add DSI controller for Qualcomm SM8750 SoC which is quite different from previous (SM8650) generation. It does not allow the display clock controller clocks like "byte" and "pixel" to be reparented to DSI PHY PLLs while the DSI PHY PLL is not configured (not prepared, rate not set). Therefore assigned-clock-parents are not working here and driver is responsible for reparenting clocks with proper procedure. These clocks are now inputs to the DSI controller device. Except that SM8750 DSI comes with several differences, new blocks and changes in registers, making it incompatible with SM8650. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/659609/ Link: https://lore.kernel.org/r/20250618-b4-sm8750-display-v7-2-a591c609743d@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
481 lines
12 KiB
YAML
481 lines
12 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display DSI controller
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maintainers:
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- Krishna Manikandan <quic_mkrishn@quicinc.com>
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- qcom,apq8064-dsi-ctrl
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- qcom,msm8226-dsi-ctrl
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- qcom,msm8916-dsi-ctrl
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- qcom,msm8953-dsi-ctrl
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- qcom,msm8974-dsi-ctrl
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- qcom,msm8976-dsi-ctrl
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- qcom,msm8996-dsi-ctrl
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- qcom,msm8998-dsi-ctrl
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- qcom,qcm2290-dsi-ctrl
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- qcom,sa8775p-dsi-ctrl
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- qcom,sar2130p-dsi-ctrl
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- qcom,sc7180-dsi-ctrl
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- qcom,sc7280-dsi-ctrl
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- qcom,sdm660-dsi-ctrl
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- qcom,sdm670-dsi-ctrl
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- qcom,sdm845-dsi-ctrl
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- qcom,sm6115-dsi-ctrl
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- qcom,sm6125-dsi-ctrl
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- qcom,sm6150-dsi-ctrl
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- qcom,sm6350-dsi-ctrl
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- qcom,sm6375-dsi-ctrl
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- qcom,sm7150-dsi-ctrl
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- qcom,sm8150-dsi-ctrl
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- qcom,sm8250-dsi-ctrl
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- qcom,sm8350-dsi-ctrl
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- qcom,sm8450-dsi-ctrl
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- qcom,sm8550-dsi-ctrl
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- qcom,sm8650-dsi-ctrl
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- qcom,sm8750-dsi-ctrl
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- const: qcom,mdss-dsi-ctrl
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- enum:
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- qcom,dsi-ctrl-6g-qcm2290
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- qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible
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deprecated: true
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reg:
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maxItems: 1
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reg-names:
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const: dsi_ctrl
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interrupts:
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maxItems: 1
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clocks:
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description: |
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Several clocks are used, depending on the variant. Typical ones are::
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- bus:: Display AHB clock.
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- byte:: Display byte clock.
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- byte_intf:: Display byte interface clock.
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- core:: Display core clock.
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- core_mss:: Core MultiMedia SubSystem clock.
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- iface:: Display AXI clock.
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- mdp_core:: MDP Core clock.
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- mnoc:: MNOC clock
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- pixel:: Display pixel clock.
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minItems: 3
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maxItems: 12
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clock-names:
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minItems: 3
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maxItems: 12
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phys:
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maxItems: 1
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phy-names:
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deprecated: true
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const: dsi
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syscon-sfpb:
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description: A phandle to mmss_sfpb syscon node (only for DSIv2).
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$ref: /schemas/types.yaml#/definitions/phandle
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qcom,dual-dsi-mode:
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type: boolean
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description: |
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Indicates if the DSI controller is driving a panel which needs
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2 DSI links.
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qcom,master-dsi:
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type: boolean
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description: |
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Indicates if the DSI controller is the master DSI controller when
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qcom,dual-dsi-mode enabled.
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qcom,sync-dual-dsi:
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type: boolean
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description: |
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Indicates if the DSI controller needs to sync the other DSI controller
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with MIPI DCS commands when qcom,dual-dsi-mode enabled.
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assigned-clocks:
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minItems: 2
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maxItems: 4
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description: |
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For DSI on SM8650 and older: parents of "byte" and "pixel" for the given
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platform.
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For DSIv2 platforms this should contain "byte", "esc", "src" and
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"pixel_src" clocks.
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assigned-clock-parents:
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minItems: 2
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maxItems: 4
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description: |
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The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.
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power-domains:
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maxItems: 1
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operating-points-v2: true
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opp-table:
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type: object
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description: |
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Contains DSI controller input and output ports as children, each
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containing one endpoint subnode.
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description: |
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Input endpoints of the controller.
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properties:
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endpoint:
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$ref: /schemas/media/video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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data-lanes:
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maxItems: 4
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minItems: 1
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items:
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enum: [ 0, 1, 2, 3 ]
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port@1:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description: |
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Output endpoints of the controller.
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properties:
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endpoint:
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$ref: /schemas/media/video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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data-lanes:
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maxItems: 4
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minItems: 1
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items:
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enum: [ 0, 1, 2, 3 ]
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qcom,te-source:
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$ref: /schemas/types.yaml#/definitions/string
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description:
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Specifies the source of vsync signal from the panel used for
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tearing elimination.
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default: mdp_vsync_p
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enum:
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- mdp_vsync_p
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- mdp_vsync_s
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- mdp_vsync_e
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- timer0
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- timer1
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- timer2
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- timer3
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- timer4
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required:
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- port@0
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- port@1
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avdd-supply:
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description:
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Phandle to vdd regulator device node
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refgen-supply:
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description:
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Phandle to REFGEN regulator device node
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vcca-supply:
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description:
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Phandle to vdd regulator device node
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vdd-supply:
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description:
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VDD regulator
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vddio-supply:
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description:
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VDD-IO regulator
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vdda-supply:
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description:
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VDDA regulator
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- clocks
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- clock-names
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- phys
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- ports
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allOf:
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- $ref: ../dsi-controller.yaml#
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,apq8064-dsi-ctrl
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then:
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properties:
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clocks:
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minItems: 7
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maxItems: 7
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clock-names:
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items:
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- const: iface
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- const: bus
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- const: core_mmss
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- const: src
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- const: byte
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- const: pixel
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- const: core
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required:
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- assigned-clocks
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- assigned-clock-parents
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,msm8916-dsi-ctrl
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- qcom,msm8953-dsi-ctrl
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- qcom,msm8976-dsi-ctrl
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then:
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properties:
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clocks:
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minItems: 6
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maxItems: 6
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clock-names:
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items:
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- const: mdp_core
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- const: iface
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- const: bus
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- const: byte
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- const: pixel
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- const: core
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required:
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- assigned-clocks
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- assigned-clock-parents
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,msm8226-dsi-ctrl
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- qcom,msm8974-dsi-ctrl
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then:
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properties:
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clocks:
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minItems: 7
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maxItems: 7
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clock-names:
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items:
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- const: mdp_core
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- const: iface
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- const: bus
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- const: byte
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- const: pixel
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- const: core
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- const: core_mmss
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required:
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- assigned-clocks
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- assigned-clock-parents
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,msm8996-dsi-ctrl
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then:
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properties:
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clocks:
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minItems: 7
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maxItems: 7
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clock-names:
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items:
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- const: mdp_core
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- const: byte
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- const: iface
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- const: bus
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- const: core_mmss
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- const: pixel
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- const: core
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required:
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- assigned-clocks
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- assigned-clock-parents
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,msm8998-dsi-ctrl
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- qcom,sa8775p-dsi-ctrl
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- qcom,sar2130p-dsi-ctrl
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- qcom,sc7180-dsi-ctrl
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- qcom,sc7280-dsi-ctrl
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- qcom,sdm845-dsi-ctrl
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- qcom,sm6115-dsi-ctrl
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- qcom,sm6125-dsi-ctrl
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- qcom,sm6350-dsi-ctrl
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- qcom,sm6375-dsi-ctrl
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- qcom,sm6150-dsi-ctrl
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- qcom,sm7150-dsi-ctrl
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- qcom,sm8150-dsi-ctrl
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- qcom,sm8250-dsi-ctrl
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- qcom,sm8350-dsi-ctrl
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- qcom,sm8450-dsi-ctrl
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- qcom,sm8550-dsi-ctrl
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- qcom,sm8650-dsi-ctrl
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then:
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properties:
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clocks:
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minItems: 6
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maxItems: 6
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clock-names:
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items:
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- const: byte
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- const: byte_intf
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- const: pixel
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- const: core
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- const: iface
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- const: bus
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required:
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- assigned-clocks
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- assigned-clock-parents
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sm8750-dsi-ctrl
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then:
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properties:
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clocks:
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minItems: 12
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maxItems: 12
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clock-names:
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items:
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- const: byte
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- const: byte_intf
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- const: pixel
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- const: core
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- const: iface
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- const: bus
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- const: dsi_pll_pixel
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- const: dsi_pll_byte
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- const: esync
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- const: osc
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- const: byte_src
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- const: pixel_src
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sdm660-dsi-ctrl
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then:
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properties:
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clocks:
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minItems: 9
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maxItems: 9
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clock-names:
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items:
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- const: mdp_core
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- const: byte
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- const: byte_intf
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- const: mnoc
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- const: iface
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- const: bus
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- const: core_mmss
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- const: pixel
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- const: core
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required:
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- assigned-clocks
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- assigned-clock-parents
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
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#include <dt-bindings/clock/qcom,gcc-sdm845.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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dsi@ae94000 {
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compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl";
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reg = <0x0ae94000 0x400>;
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reg-names = "dsi_ctrl";
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&mdss>;
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interrupts = <4>;
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clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
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<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
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<&dispcc DISP_CC_MDSS_ESC0_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_AXI_CLK>;
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clock-names = "byte",
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"byte_intf",
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"pixel",
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"core",
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"iface",
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"bus";
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phys = <&dsi0_phy>;
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phy-names = "dsi";
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assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
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assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
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power-domains = <&rpmhpd SC7180_CX>;
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operating-points-v2 = <&dsi_opp_table>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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endpoint {
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remote-endpoint = <&dpu_intf1_out>;
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};
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};
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port@1 {
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reg = <1>;
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endpoint {
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remote-endpoint = <&sn65dsi86_in>;
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data-lanes = <0 1 2 3>;
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qcom,te-source = "mdp_vsync_e";
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};
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};
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};
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};
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...
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