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0121898ec0
DTS example in the bindings should be indented with 2- or 4-spaces and aligned with opening '- |', so correct any differences like 3-spaces or mixtures 2- and 4-spaces in one binding. No functional changes here, but saves some comments during reviews of new patches built on existing code. Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # For MMC Acked-by: Lee Jones <lee@kernel.org> Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> # renesas Link: https://lore.kernel.org/r/20250107131456.247610-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250725100241.120106-2-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
51 lines
1.2 KiB
YAML
51 lines
1.2 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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# Copyright 2021, Arm Ltd
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/arm,trace-buffer-extension.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM Trace Buffer Extensions
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maintainers:
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- Anshuman Khandual <anshuman.khandual@arm.com>
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description: |
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Arm Trace Buffer Extension (TRBE) is a per CPU component
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for storing trace generated on the CPU to memory. It is
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accessed via CPU system registers. The software can verify
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if it is permitted to use the component by checking the
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TRBIDR register.
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properties:
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$nodename:
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const: trbe
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compatible:
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items:
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- const: arm,trace-buffer-extension
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interrupts:
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description: |
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Exactly 1 PPI must be listed. For heterogeneous systems where
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TRBE is only supported on a subset of the CPUs, please consult
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the arm,gic-v3 binding for details on describing a PPI partition.
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maxItems: 1
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required:
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- compatible
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- interrupts
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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trbe {
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compatible = "arm,trace-buffer-extension";
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interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
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};
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...
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