Commit Graph

5 Commits

Author SHA1 Message Date
Srinivas Pandruvada
5aa63cab70 tools/power/x86/intel-speed-select: Support SST PP revision 2 fields
Display fields added by SST PP revision 2. They include:
uncore P0 (max frequency), P1 (base frequency) and Pm (min frequency)
for uncore fabric 1.

Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2025-05-09 10:58:39 -07:00
Srinivas Pandruvada
991c8aacfb tools/power/x86/intel-speed-select: Fix TRL restore after SST-TF disable
When SST-TF is disabled, the TRL (Turbo Ratio Limit) of config level 0
is getting restored. But the TRL of current level should be restored
which may not be config level 0.

This is caused by a bug in treating config level as TRL level. So
arguments needs to be swapped.

Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2025-01-03 06:29:02 -08:00
Srinivas Pandruvada
1fcf670e50 tools/power/x86/intel-speed-select: SST BF/TF support per level
SST BF and TF can be enabled/disabled per level. So check the current
level support from the mask of supported levels.

This change from a single level to mask for info.sst_tf_support and
info.sst_tf_support is indicated by API version change. Use as mask for
API version above 2. In this way there is no change in behavior when
running on older kernel with API version 2.

Since the tool can support now API version 3, update the supported API
version.

Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2024-04-29 13:31:50 +02:00
Srinivas Pandruvada
4ebde55b7d tools/power/x86/intel-speed-select: Adjust scope of core-power config
When core-power configuration or enabled is modified, this is only done
for compute dies. But the config must also be set to cores with no CPUs.
Without this the configuration is not affective.

On displaying config information, allow display for non compute dies
also.

Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-06-12 16:03:25 -07:00
Zhang Rui
79554aaa22 tools/power/x86/intel-speed-select: Introduce TPMI interface support
TPMI (Topology Aware Register and PM Capsule Interface) creates a
flexible, extendable and software-PCIe-driver-enumerable MMIO interface
for PM features.

SST feature is exposed via the TPMI interface on newer Xeon platforms.

Kernel TPMI based SST driver provides a series of new IOCTLs for userspace
to use.

Introduce support for the platforms that do SST control via TPMI interface.

Compared with previous platforms, Newer Xeons also supports multi-punit in a
package/die, including cpu punit and non-cpu punit. These have already
been handled in the generic code.

Signed-off-by: Zhang Rui <rui.zhang@intel.com>
[srinivas.pandruvada@linux.intel.com: changelog edits]
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22 13:36:54 -07:00