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drm/xe: map MMIO BAR according to the num of tiles in device desc

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When MMIO BAR is initially mapped, the driver assumes a single tile device.
However, former memory allocations take all tiles into account.
First, a common standard for resource usage is needed here.
Second, with the next (6th) patch in this series, the MMIO BAR remapping
will be done only if a reduced-tile device is attached.

Signed-off-by: Koby Elbaz <kelbaz@habana.ai>
Reviewed-by: Ofir Bitton <obitton@habana.ai>
Reviewed-by: Moti Haimovski <mhaimovski@habana.ai>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Koby Elbaz 2023-10-05 11:06:18 -04:00 committed by Rodrigo Vivi
parent 866b2b1764
commit ef29b390c7
1 changed files with 6 additions and 7 deletions
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13
drivers/gpu/drm/xe/xe_mmio.c
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@ -383,14 +383,13 @@ int xe_mmio_init(struct xe_device *xe)
int err;
/*
* Map the first 16MB of th BAR, which includes the registers (0-4MB),
* reserved space (4MB-8MB), and GGTT (8MB-16MB) for a single tile.
* This will get remapped later if we determine that we're running
* on a multi-tile system.
* Map the maximum expected BAR size, which will get remapped later
* if we determine that we're running on a reduced-tile system.
* The first 16MB of the BAR, belong to the root tile, and include:
* registers (0-4MB), reserved space (4MB-8MB) and GGTT (8MB-16MB).
*/
xe->mmio.size = SZ_16M;
xe->mmio.regs = pci_iomap(to_pci_dev(xe->drm.dev), mmio_bar,
xe->mmio.size);
xe->mmio.size = (SZ_16M + xe->info.tile_mmio_ext_size) * xe->info.tile_count;
xe->mmio.regs = pci_iomap(to_pci_dev(xe->drm.dev), mmio_bar, xe->mmio.size);
if (xe->mmio.regs == NULL) {
drm_err(&xe->drm, "failed to map registers\n");
return -EIO;