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ARM: dts: amlogic: meson8b: switch to the new PWM controller binding
Use the new PWM controller binding which now relies on passing all clock inputs available on the SoC (instead of passing the "wanted" clock input for a given board). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241227212514.1376682-3-martin.blumenstingl@googlemail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
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@ -443,8 +443,6 @@ &pwm_cd {
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status = "okay";
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pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;
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pinctrl-names = "default";
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clocks = <&xtal>, <&xtal>;
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clock-names = "clkin0", "clkin1";
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};
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&rtc {
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@ -162,8 +162,6 @@ &pwm_cd {
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status = "okay";
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pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;
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pinctrl-names = "default";
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clocks = <&xtal>, <&xtal>;
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clock-names = "clkin0", "clkin1";
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};
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&uart_AO {
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@ -347,8 +347,6 @@ &pwm_cd {
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status = "okay";
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pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>;
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pinctrl-names = "default";
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clocks = <&xtal>, <&xtal>;
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clock-names = "clkin0", "clkin1";
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};
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&rtc {
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@ -403,8 +403,12 @@ analog_top: analog-top@81a8 {
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};
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pwm_ef: pwm@86c0 {
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compatible = "amlogic,meson8b-pwm";
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compatible = "amlogic,meson8b-pwm-v2", "amlogic,meson8-pwm-v2";
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reg = <0x86c0 0x10>;
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clocks = <&xtal>,
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<>, /* unknown/untested, the datasheet calls it "Video PLL" */
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<&clkc CLKID_FCLK_DIV4>,
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<&clkc CLKID_FCLK_DIV3>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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@ -674,11 +678,19 @@ timer@600 {
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};
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&pwm_ab {
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compatible = "amlogic,meson8b-pwm";
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compatible = "amlogic,meson8b-pwm-v2", "amlogic,meson8-pwm-v2";
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clocks = <&xtal>,
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<>, /* unknown/untested, the datasheet calls it "Video PLL" */
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<&clkc CLKID_FCLK_DIV4>,
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<&clkc CLKID_FCLK_DIV3>;
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};
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&pwm_cd {
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compatible = "amlogic,meson8b-pwm";
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compatible = "amlogic,meson8b-pwm-v2", "amlogic,meson8-pwm-v2";
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clocks = <&xtal>,
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<>, /* unknown/untested, the datasheet calls it "Video PLL" */
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<&clkc CLKID_FCLK_DIV4>,
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<&clkc CLKID_FCLK_DIV3>;
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};
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&rtc {
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