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drm/amdgpu: add dynamic workload profile switching for gfx10

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Enable dynamic workload profile switching for gfx10.

Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2025-01-08 17:32:31 -05:00
parent 8fdb3958e3
commit b9467983b7
1 changed files with 22 additions and 4 deletions
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26
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
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@ -4701,6 +4701,8 @@ static int gfx_v10_0_sw_init(struct amdgpu_ip_block *ip_block)
int xcc_id = 0; int xcc_id = 0;
struct amdgpu_device *adev = ip_block->adev; struct amdgpu_device *adev = ip_block->adev;
INIT_DELAYED_WORK(&adev->gfx.idle_work, amdgpu_gfx_profile_idle_work_handler);
switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
case IP_VERSION(10, 1, 10): case IP_VERSION(10, 1, 10):
case IP_VERSION(10, 1, 1): case IP_VERSION(10, 1, 1):
@ -7467,6 +7469,8 @@ static int gfx_v10_0_hw_fini(struct amdgpu_ip_block *ip_block)
{ {
struct amdgpu_device *adev = ip_block->adev; struct amdgpu_device *adev = ip_block->adev;
cancel_delayed_work_sync(&adev->gfx.idle_work);
amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0);
@ -9748,6 +9752,20 @@ static void gfx_v10_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring)
amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */
} }
static void gfx_v10_0_ring_begin_use(struct amdgpu_ring *ring)
{
amdgpu_gfx_profile_ring_begin_use(ring);
amdgpu_gfx_enforce_isolation_ring_begin_use(ring);
}
static void gfx_v10_0_ring_end_use(struct amdgpu_ring *ring)
{
amdgpu_gfx_profile_ring_end_use(ring);
amdgpu_gfx_enforce_isolation_ring_end_use(ring);
}
static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
.name = "gfx_v10_0", .name = "gfx_v10_0",
.early_init = gfx_v10_0_early_init, .early_init = gfx_v10_0_early_init,
@ -9823,8 +9841,8 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
.emit_mem_sync = gfx_v10_0_emit_mem_sync, .emit_mem_sync = gfx_v10_0_emit_mem_sync,
.reset = gfx_v10_0_reset_kgq, .reset = gfx_v10_0_reset_kgq,
.emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader, .emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader,
.begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use, .begin_use = gfx_v10_0_ring_begin_use,
.end_use = amdgpu_gfx_enforce_isolation_ring_end_use, .end_use = gfx_v10_0_ring_end_use,
}; };
static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
@ -9864,8 +9882,8 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
.emit_mem_sync = gfx_v10_0_emit_mem_sync, .emit_mem_sync = gfx_v10_0_emit_mem_sync,
.reset = gfx_v10_0_reset_kcq, .reset = gfx_v10_0_reset_kcq,
.emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader, .emit_cleaner_shader = gfx_v10_0_ring_emit_cleaner_shader,
.begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use, .begin_use = gfx_v10_0_ring_begin_use,
.end_use = amdgpu_gfx_enforce_isolation_ring_end_use, .end_use = gfx_v10_0_ring_end_use,
}; };
static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {