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pinctrl: renesas: rzg2l: Add support for RZ/V2H SoC
Add pinctrl driver support for RZ/V2H(P) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240530173857.164073-16-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Lad Prabhakar
Geert Uytterhoeven
parent
fb73d663b3
commit
9bd95ac86e
@ -59,6 +59,10 @@
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#define PIN_CFG_OEN BIT(15)
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#define PIN_CFG_VARIABLE BIT(16)
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#define PIN_CFG_NOGPIO_INT BIT(17)
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#define PIN_CFG_NOD BIT(18) /* N-ch Open Drain */
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#define PIN_CFG_SMT BIT(19) /* Schmitt-trigger input control */
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#define PIN_CFG_ELC BIT(20)
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#define PIN_CFG_IOLH_RZV2H BIT(21)
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#define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \
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(PIN_CFG_IOLH_##group | \
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@ -73,6 +77,11 @@
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#define RZG3S_MPXED_PIN_FUNCS(group) (RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \
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PIN_CFG_SOFT_PS)
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#define RZV2H_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) | \
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PIN_CFG_NOD | \
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PIN_CFG_SR | \
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PIN_CFG_SMT)
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#define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | \
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PIN_CFG_FILONOFF | \
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PIN_CFG_FILNUM | \
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@ -135,6 +144,7 @@
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#define ETH_POC(off, ch) ((off) + (ch) * 4)
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#define QSPI (0x3008)
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#define ETH_MODE (0x3018)
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#define PFC_OEN (0x3C40) /* known on RZ/V2H(P) only */
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#define PVDD_2500 2 /* I/O domain voltage 2.5V */
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#define PVDD_1800 1 /* I/O domain voltage <= 1.8V */
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@ -142,6 +152,8 @@
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#define PWPR_B0WI BIT(7) /* Bit Write Disable */
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#define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */
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#define PWPR_REGWE_A BIT(6) /* PFC and PMC Register Write Enable on RZ/V2H(P) */
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#define PWPR_REGWE_B BIT(5) /* OEN Register Write Enable, known only in RZ/V2H(P) */
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#define PM_MASK 0x03
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#define PFC_MASK 0x07
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@ -160,6 +172,19 @@
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#define RZG2L_TINT_IRQ_START_INDEX 9
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#define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i))
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/* Custom pinconf parameters */
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#define RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE (PIN_CONFIG_END + 1)
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static const struct pinconf_generic_params renesas_rzv2h_custom_bindings[] = {
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{ "renesas,output-impedance", RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, 1 },
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};
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#ifdef CONFIG_DEBUG_FS
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static const struct pin_config_item renesas_rzv2h_conf_items[] = {
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PCONFDUMP(RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, "output-impedance", "x", true),
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};
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#endif
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/* Read/write 8 bits register */
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#define RZG2L_PCTRL_REG_ACCESS8(_read, _addr, _val) \
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do { \
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@ -352,6 +377,15 @@ static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl,
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return 0;
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}
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static const u64 r9a09g057_variable_pin_cfg[] = {
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RZG2L_VARIABLE_PIN_CFG_PACK(11, 0, RZV2H_MPXED_PIN_FUNCS),
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RZG2L_VARIABLE_PIN_CFG_PACK(11, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
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RZG2L_VARIABLE_PIN_CFG_PACK(11, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
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RZG2L_VARIABLE_PIN_CFG_PACK(11, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
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RZG2L_VARIABLE_PIN_CFG_PACK(11, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
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RZG2L_VARIABLE_PIN_CFG_PACK(11, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
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};
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#ifdef CONFIG_RISCV
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static const u64 r9a07g043f_variable_pin_cfg[] = {
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RZG2L_VARIABLE_PIN_CFG_PACK(20, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
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@ -402,6 +436,17 @@ static void rzg2l_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset)
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writeb(val, pctrl->base + offset);
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}
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static void rzv2h_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset)
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{
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const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;
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u8 pwpr;
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pwpr = readb(pctrl->base + regs->pwpr);
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writeb(pwpr | PWPR_REGWE_A, pctrl->base + regs->pwpr);
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writeb(val, pctrl->base + offset);
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writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr);
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}
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static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
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u8 pin, u8 off, u8 func)
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{
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@ -1041,14 +1086,104 @@ static int rzg2l_bias_param_to_hw(enum pin_config_param param)
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return -EINVAL;
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}
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static int rzv2h_hw_to_bias_param(unsigned int bias)
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{
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switch (bias) {
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case 0:
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case 1:
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return PIN_CONFIG_BIAS_DISABLE;
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case 2:
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return PIN_CONFIG_BIAS_PULL_DOWN;
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case 3:
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return PIN_CONFIG_BIAS_PULL_UP;
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default:
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break;
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}
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return -EINVAL;
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}
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static int rzv2h_bias_param_to_hw(enum pin_config_param param)
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{
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switch (param) {
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case PIN_CONFIG_BIAS_DISABLE:
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return 0;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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return 2;
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case PIN_CONFIG_BIAS_PULL_UP:
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return 3;
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default:
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break;
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}
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return -EINVAL;
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}
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static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, u32 offset)
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{
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static const char * const pin_names[] = { "ET0_TXC_TXCLK", "ET1_TXC_TXCLK",
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"XSPI0_RESET0N", "XSPI0_CS0N",
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"XSPI0_CKN", "XSPI0_CKP" };
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const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(pin_names); i++) {
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if (!strcmp(pin_desc->name, pin_names[i]))
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return i;
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}
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/* Should not happen. */
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return 0;
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}
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static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin)
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{
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u8 bit;
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if (!(caps & PIN_CFG_OEN))
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return 0;
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bit = rzv2h_pin_to_oen_bit(pctrl, offset);
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return !(readb(pctrl->base + PFC_OEN) & BIT(bit));
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}
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static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen)
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{
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const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
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const struct rzg2l_register_offsets *regs = &hwcfg->regs;
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unsigned long flags;
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u8 val, bit;
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u8 pwpr;
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if (!(caps & PIN_CFG_OEN))
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return -EINVAL;
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bit = rzv2h_pin_to_oen_bit(pctrl, offset);
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spin_lock_irqsave(&pctrl->lock, flags);
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val = readb(pctrl->base + PFC_OEN);
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if (oen)
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val &= ~BIT(bit);
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else
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val |= BIT(bit);
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pwpr = readb(pctrl->base + regs->pwpr);
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writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr);
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writeb(val, pctrl->base + PFC_OEN);
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writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr);
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spin_unlock_irqrestore(&pctrl->lock, flags);
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return 0;
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}
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static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
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unsigned int _pin,
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unsigned long *config)
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{
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struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
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enum pin_config_param param = pinconf_to_config_param(*config);
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const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
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const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
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u32 param = pinconf_to_config_param(*config);
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u64 *pin_data = pin->drv_data;
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unsigned int arg = 0;
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u32 off;
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@ -1159,6 +1294,13 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
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break;
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}
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case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE:
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if (!(cfg & PIN_CFG_IOLH_RZV2H))
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return -EINVAL;
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arg = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);
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break;
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default:
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return -ENOTSUPP;
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}
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@ -1178,9 +1320,8 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
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const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
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struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin];
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u64 *pin_data = pin->drv_data;
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enum pin_config_param param;
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unsigned int i, arg, index;
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u32 off;
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u32 off, param;
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u64 cfg;
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int ret;
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u8 bit;
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@ -1285,6 +1426,16 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
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rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index);
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break;
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case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE:
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if (!(cfg & PIN_CFG_IOLH_RZV2H))
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return -EINVAL;
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arg = pinconf_to_config_argument(_configs[i]);
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if (arg > 3)
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return -EINVAL;
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rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, arg);
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break;
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default:
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return -EOPNOTSUPP;
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}
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@ -1732,6 +1883,39 @@ static const u64 r9a08g045_gpio_configs[] = {
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RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)), /* P18 */
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};
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static const char * const rzv2h_gpio_names[] = {
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"P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07",
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"P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17",
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"P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27",
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"P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37",
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"P40", "P41", "P42", "P43", "P44", "P45", "P46", "P47",
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"P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57",
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"P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67",
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"P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77",
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"P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87",
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"P90", "P91", "P92", "P93", "P94", "P95", "P96", "P97",
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"PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7",
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"PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7",
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};
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static const u64 r9a09g057_gpio_configs[] = {
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RZG2L_GPIO_PORT_PACK(8, 0x20, RZV2H_MPXED_PIN_FUNCS), /* P0 */
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RZG2L_GPIO_PORT_PACK(6, 0x21, RZV2H_MPXED_PIN_FUNCS), /* P1 */
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RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) |
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PIN_CFG_NOD), /* P2 */
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RZG2L_GPIO_PORT_PACK(8, 0x23, RZV2H_MPXED_PIN_FUNCS), /* P3 */
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RZG2L_GPIO_PORT_PACK(8, 0x24, RZV2H_MPXED_PIN_FUNCS), /* P4 */
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RZG2L_GPIO_PORT_PACK(8, 0x25, RZV2H_MPXED_PIN_FUNCS), /* P5 */
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RZG2L_GPIO_PORT_PACK(8, 0x26, RZV2H_MPXED_PIN_FUNCS |
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PIN_CFG_ELC), /* P6 */
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RZG2L_GPIO_PORT_PACK(8, 0x27, RZV2H_MPXED_PIN_FUNCS), /* P7 */
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RZG2L_GPIO_PORT_PACK(8, 0x28, RZV2H_MPXED_PIN_FUNCS |
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PIN_CFG_ELC), /* P8 */
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RZG2L_GPIO_PORT_PACK(8, 0x29, RZV2H_MPXED_PIN_FUNCS), /* P9 */
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RZG2L_GPIO_PORT_PACK(8, 0x2a, RZV2H_MPXED_PIN_FUNCS), /* PA */
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RZG2L_GPIO_PORT_PACK(6, 0x2b, PIN_CFG_VARIABLE), /* PB */
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};
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static const struct {
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struct rzg2l_dedicated_configs common[35];
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struct rzg2l_dedicated_configs rzg2l_pins[7];
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@ -1858,6 +2042,138 @@ static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = {
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PIN_CFG_IO_VMC_SD1)) },
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};
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static struct rzg2l_dedicated_configs rzv2h_dedicated_pins[] = {
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{ "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_FILONOFF | PIN_CFG_FILNUM |
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PIN_CFG_FILCLKSEL)) },
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{ "TMS_SWDIO", RZG2L_SINGLE_PIN_PACK(0x3, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
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PIN_CFG_IEN)) },
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{ "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
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{ "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
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PIN_CFG_PUPD | PIN_CFG_NOD)) },
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{ "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
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PIN_CFG_PUPD | PIN_CFG_NOD)) },
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{ "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
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PIN_CFG_PUPD)) },
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{ "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
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PIN_CFG_PUPD)) },
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{ "XSPI0_CKP", RZG2L_SINGLE_PIN_PACK(0x7, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
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PIN_CFG_PUPD | PIN_CFG_OEN)) },
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{ "XSPI0_CKN", RZG2L_SINGLE_PIN_PACK(0x7, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
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PIN_CFG_PUPD | PIN_CFG_OEN)) },
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{ "XSPI0_CS0N", RZG2L_SINGLE_PIN_PACK(0x7, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
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PIN_CFG_PUPD | PIN_CFG_OEN)) },
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{ "XSPI0_DS", RZG2L_SINGLE_PIN_PACK(0x7, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
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PIN_CFG_PUPD)) },
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{ "XSPI0_RESET0N", RZG2L_SINGLE_PIN_PACK(0x7, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
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PIN_CFG_PUPD | PIN_CFG_OEN)) },
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{ "XSPI0_RSTO0N", RZG2L_SINGLE_PIN_PACK(0x7, 5, (PIN_CFG_PUPD)) },
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{ "XSPI0_INT0N", RZG2L_SINGLE_PIN_PACK(0x7, 6, (PIN_CFG_PUPD)) },
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{ "XSPI0_ECS0N", RZG2L_SINGLE_PIN_PACK(0x7, 7, (PIN_CFG_PUPD)) },
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{ "XSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0x8, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
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PIN_CFG_PUPD)) },
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{ "XSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0x8, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
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PIN_CFG_PUPD)) },
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{ "XSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0x8, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
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PIN_CFG_PUPD)) },
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{ "XSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0x8, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
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PIN_CFG_PUPD)) },
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{ "XSPI0_IO4", RZG2L_SINGLE_PIN_PACK(0x8, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
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PIN_CFG_PUPD)) },
|
||||
{ "XSPI0_IO5", RZG2L_SINGLE_PIN_PACK(0x8, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "XSPI0_IO6", RZG2L_SINGLE_PIN_PACK(0x8, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "XSPI0_IO7", RZG2L_SINGLE_PIN_PACK(0x8, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
|
||||
{ "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
|
||||
{ "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD1CLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
|
||||
{ "SD1CMD", RZG2L_SINGLE_PIN_PACK(0xb, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD1DAT0", RZG2L_SINGLE_PIN_PACK(0xc, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD1DAT1", RZG2L_SINGLE_PIN_PACK(0xc, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD1DAT2", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD1DAT3", RZG2L_SINGLE_PIN_PACK(0xc, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "PCIE0_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
|
||||
{ "PCIE1_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
|
||||
{ "ET0_MDIO", RZG2L_SINGLE_PIN_PACK(0xf, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "ET0_MDC", RZG2L_SINGLE_PIN_PACK(0xf, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET0_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_PUPD)) },
|
||||
{ "ET0_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET0_TXER", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET0_RXER", RZG2L_SINGLE_PIN_PACK(0x10, 3, (PIN_CFG_PUPD)) },
|
||||
{ "ET0_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 4, (PIN_CFG_PUPD)) },
|
||||
{ "ET0_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD | PIN_CFG_OEN)) },
|
||||
{ "ET0_CRS", RZG2L_SINGLE_PIN_PACK(0x10, 6, (PIN_CFG_PUPD)) },
|
||||
{ "ET0_COL", RZG2L_SINGLE_PIN_PACK(0x10, 7, (PIN_CFG_PUPD)) },
|
||||
{ "ET0_TXD0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET0_TXD1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET0_TXD2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET0_TXD3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET0_RXD0", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_PUPD)) },
|
||||
{ "ET0_RXD1", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_PUPD)) },
|
||||
{ "ET0_RXD2", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_PUPD)) },
|
||||
{ "ET0_RXD3", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_PUPD)) },
|
||||
{ "ET1_MDIO", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "ET1_MDC", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET1_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_PUPD)) },
|
||||
{ "ET1_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET1_TXER", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET1_RXER", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_PUPD)) },
|
||||
{ "ET1_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 4, (PIN_CFG_PUPD)) },
|
||||
{ "ET1_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD | PIN_CFG_OEN)) },
|
||||
{ "ET1_CRS", RZG2L_SINGLE_PIN_PACK(0x13, 6, (PIN_CFG_PUPD)) },
|
||||
{ "ET1_COL", RZG2L_SINGLE_PIN_PACK(0x13, 7, (PIN_CFG_PUPD)) },
|
||||
{ "ET1_TXD0", RZG2L_SINGLE_PIN_PACK(0x14, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET1_TXD1", RZG2L_SINGLE_PIN_PACK(0x14, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET1_TXD2", RZG2L_SINGLE_PIN_PACK(0x14, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET1_TXD3", RZG2L_SINGLE_PIN_PACK(0x14, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET1_RXD0", RZG2L_SINGLE_PIN_PACK(0x14, 4, (PIN_CFG_PUPD)) },
|
||||
{ "ET1_RXD1", RZG2L_SINGLE_PIN_PACK(0x14, 5, (PIN_CFG_PUPD)) },
|
||||
{ "ET1_RXD2", RZG2L_SINGLE_PIN_PACK(0x14, 6, (PIN_CFG_PUPD)) },
|
||||
{ "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) },
|
||||
};
|
||||
|
||||
static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl)
|
||||
{
|
||||
const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq];
|
||||
@ -2394,6 +2710,9 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
|
||||
BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT >
|
||||
ARRAY_SIZE(rzg2l_gpio_names));
|
||||
|
||||
BUILD_BUG_ON(ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT >
|
||||
ARRAY_SIZE(rzv2h_gpio_names));
|
||||
|
||||
pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
|
||||
if (!pctrl)
|
||||
return -ENOMEM;
|
||||
@ -2665,6 +2984,22 @@ static void rzg2l_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl *pctrl, bool lock)
|
||||
}
|
||||
}
|
||||
|
||||
static void rzv2h_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl *pctrl, bool lock)
|
||||
{
|
||||
const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;
|
||||
u8 pwpr;
|
||||
|
||||
if (lock) {
|
||||
/* Set the PWPR register to be write-protected */
|
||||
pwpr = readb(pctrl->base + regs->pwpr);
|
||||
writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr);
|
||||
} else {
|
||||
/* Set the PWPR register to allow PFC and PMC register to write */
|
||||
pwpr = readb(pctrl->base + regs->pwpr);
|
||||
writeb(PWPR_REGWE_A | pwpr, pctrl->base + regs->pwpr);
|
||||
}
|
||||
}
|
||||
|
||||
static const struct rzg2l_hwcfg rzg2l_hwcfg = {
|
||||
.regs = {
|
||||
.pwpr = 0x3014,
|
||||
@ -2710,6 +3045,12 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg = {
|
||||
.oen_max_port = 7, /* P7_1 is the maximum OEN port. */
|
||||
};
|
||||
|
||||
static const struct rzg2l_hwcfg rzv2h_hwcfg = {
|
||||
.regs = {
|
||||
.pwpr = 0x3c04,
|
||||
},
|
||||
};
|
||||
|
||||
static struct rzg2l_pinctrl_data r9a07g043_data = {
|
||||
.port_pins = rzg2l_gpio_names,
|
||||
.port_pin_configs = r9a07g043_gpio_configs,
|
||||
@ -2763,6 +3104,29 @@ static struct rzg2l_pinctrl_data r9a08g045_data = {
|
||||
.bias_param_to_hw = &rzg2l_bias_param_to_hw,
|
||||
};
|
||||
|
||||
static struct rzg2l_pinctrl_data r9a09g057_data = {
|
||||
.port_pins = rzv2h_gpio_names,
|
||||
.port_pin_configs = r9a09g057_gpio_configs,
|
||||
.n_ports = ARRAY_SIZE(r9a09g057_gpio_configs),
|
||||
.dedicated_pins = rzv2h_dedicated_pins,
|
||||
.n_port_pins = ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT,
|
||||
.n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins),
|
||||
.hwcfg = &rzv2h_hwcfg,
|
||||
.variable_pin_cfg = r9a09g057_variable_pin_cfg,
|
||||
.n_variable_pin_cfg = ARRAY_SIZE(r9a09g057_variable_pin_cfg),
|
||||
.num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings),
|
||||
.custom_params = renesas_rzv2h_custom_bindings,
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
.custom_conf_items = renesas_rzv2h_conf_items,
|
||||
#endif
|
||||
.pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,
|
||||
.pmc_writeb = &rzv2h_pmc_writeb,
|
||||
.oen_read = &rzv2h_oen_read,
|
||||
.oen_write = &rzv2h_oen_write,
|
||||
.hw_to_bias_param = &rzv2h_hw_to_bias_param,
|
||||
.bias_param_to_hw = &rzv2h_bias_param_to_hw,
|
||||
};
|
||||
|
||||
static const struct of_device_id rzg2l_pinctrl_of_table[] = {
|
||||
{
|
||||
.compatible = "renesas,r9a07g043-pinctrl",
|
||||
@ -2776,6 +3140,10 @@ static const struct of_device_id rzg2l_pinctrl_of_table[] = {
|
||||
.compatible = "renesas,r9a08g045-pinctrl",
|
||||
.data = &r9a08g045_data,
|
||||
},
|
||||
{
|
||||
.compatible = "renesas,r9a09g057-pinctrl",
|
||||
.data = &r9a09g057_data,
|
||||
},
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user