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gpio: Enable Blaize BLZP1600 GPIO support
Blaize BLZP1600 GPIO controller is provided by VeriSilicon Microelectronics based on the GPIO APB v0.2 design. It has 32 input/output ports which can be configured as edge or level triggered interrupts. It also provides a de-bounce feature. This controller is used on the Blaize BLZP1600 SoC. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com> Link: https://lore.kernel.org/r/20250327-kernel-upstreaming-add_gpio_support-v2-2-bbe51f8d66da@blaize.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
This commit is contained in:
Nikolaos Pasaloukos
Bartosz Golaszewski
parent
338893af8e
commit
602ae04f56
10
MAINTAINERS
10
MAINTAINERS
@ -4195,6 +4195,16 @@ F: Documentation/ABI/stable/sysfs-class-bluetooth
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F: include/net/bluetooth/
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F: net/bluetooth/
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BLZP1600 GPIO DRIVER
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M: James Cowgill <james.cowgill@blaize.com>
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M: Matt Redfearn <matt.redfearn@blaize.com>
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M: Neil Jones <neil.jones@blaize.com>
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M: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
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L: linux-gpio@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/gpio/blaize,blzp1600-gpio.yaml
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F: drivers/gpio/gpio-blzp1600.c
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BONDING DRIVER
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M: Jay Vosburgh <jv@jvosburgh.net>
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L: netdev@vger.kernel.org
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@ -213,6 +213,17 @@ config GPIO_BCM_XGS_IPROC
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help
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Say yes here to enable GPIO support for Broadcom XGS iProc SoCs.
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config GPIO_BLZP1600
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tristate "Blaize BLZP1600 GPIO support"
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default y if ARCH_BLAIZE
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depends on OF_GPIO
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select GPIO_GENERIC
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select GPIOLIB_IRQCHIP
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help
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Say Y or M here to add support for the Blaize BLZP1600 GPIO device.
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The controller is based on the Verisilicon Microelectronics GPIO APB v0.2
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IP block.
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config GPIO_BRCMSTB
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tristate "BRCMSTB GPIO support"
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default y if (ARCH_BRCMSTB || BMIPS_GENERIC)
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@ -45,6 +45,7 @@ obj-$(CONFIG_GPIO_BCM_XGS_IPROC) += gpio-xgs-iproc.o
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obj-$(CONFIG_GPIO_BD71815) += gpio-bd71815.o
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obj-$(CONFIG_GPIO_BD71828) += gpio-bd71828.o
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obj-$(CONFIG_GPIO_BD9571MWV) += gpio-bd9571mwv.o
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obj-$(CONFIG_GPIO_BLZP1600) += gpio-blzp1600.o
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obj-$(CONFIG_GPIO_BRCMSTB) += gpio-brcmstb.o
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obj-$(CONFIG_GPIO_BT8XX) += gpio-bt8xx.o
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obj-$(CONFIG_GPIO_CADENCE) += gpio-cadence.o
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283
drivers/gpio/gpio-blzp1600.c
Normal file
283
drivers/gpio/gpio-blzp1600.c
Normal file
@ -0,0 +1,283 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2019 VeriSilicon Limited.
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* Copyright (C) 2025 Blaize, Inc.
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*/
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#include <linux/errno.h>
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#include <linux/gpio/driver.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#define GPIO_DIR_REG 0x00
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#define GPIO_CTRL_REG 0x04
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#define GPIO_SET_REG 0x08
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#define GPIO_CLR_REG 0x0C
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#define GPIO_ODATA_REG 0x10
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#define GPIO_IDATA_REG 0x14
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#define GPIO_IEN_REG 0x18
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#define GPIO_IS_REG 0x1C
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#define GPIO_IBE_REG 0x20
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#define GPIO_IEV_REG 0x24
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#define GPIO_RIS_REG 0x28
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#define GPIO_IM_REG 0x2C
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#define GPIO_MIS_REG 0x30
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#define GPIO_IC_REG 0x34
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#define GPIO_DB_REG 0x38
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#define GPIO_DFG_REG 0x3C
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#define DRIVER_NAME "blzp1600-gpio"
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struct blzp1600_gpio {
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void __iomem *base;
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struct gpio_chip gc;
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int irq;
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};
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static inline struct blzp1600_gpio *get_blzp1600_gpio_from_irq_data(struct irq_data *d)
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{
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return gpiochip_get_data(irq_data_get_irq_chip_data(d));
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}
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static inline struct blzp1600_gpio *get_blzp1600_gpio_from_irq_desc(struct irq_desc *d)
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{
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return gpiochip_get_data(irq_desc_get_handler_data(d));
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}
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static inline u32 blzp1600_gpio_read(struct blzp1600_gpio *chip, unsigned int offset)
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{
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return readl_relaxed(chip->base + offset);
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}
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static inline void blzp1600_gpio_write(struct blzp1600_gpio *chip, unsigned int offset, u32 val)
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{
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writel_relaxed(val, chip->base + offset);
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}
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static inline void blzp1600_gpio_rmw(void __iomem *reg, u32 mask, bool set)
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{
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u32 val = readl_relaxed(reg);
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if (set)
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val |= mask;
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else
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val &= ~mask;
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writel_relaxed(val, reg);
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}
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static void blzp1600_gpio_irq_mask(struct irq_data *d)
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{
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struct blzp1600_gpio *chip = get_blzp1600_gpio_from_irq_data(d);
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guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock);
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blzp1600_gpio_rmw(chip->base + GPIO_IM_REG, BIT(d->hwirq), 1);
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}
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static void blzp1600_gpio_irq_unmask(struct irq_data *d)
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{
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struct blzp1600_gpio *chip = get_blzp1600_gpio_from_irq_data(d);
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guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock);
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blzp1600_gpio_rmw(chip->base + GPIO_IM_REG, BIT(d->hwirq), 0);
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}
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static void blzp1600_gpio_irq_ack(struct irq_data *d)
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{
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struct blzp1600_gpio *chip = get_blzp1600_gpio_from_irq_data(d);
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blzp1600_gpio_write(chip, GPIO_IC_REG, BIT(d->hwirq));
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}
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static void blzp1600_gpio_irq_enable(struct irq_data *d)
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{
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struct blzp1600_gpio *chip = get_blzp1600_gpio_from_irq_data(d);
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gpiochip_enable_irq(&chip->gc, irqd_to_hwirq(d));
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guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock);
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blzp1600_gpio_rmw(chip->base + GPIO_DIR_REG, BIT(d->hwirq), 0);
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blzp1600_gpio_rmw(chip->base + GPIO_IEN_REG, BIT(d->hwirq), 1);
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}
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static void blzp1600_gpio_irq_disable(struct irq_data *d)
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{
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struct blzp1600_gpio *chip = get_blzp1600_gpio_from_irq_data(d);
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guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock);
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blzp1600_gpio_rmw(chip->base + GPIO_IEN_REG, BIT(d->hwirq), 0);
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gpiochip_disable_irq(&chip->gc, irqd_to_hwirq(d));
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}
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static int blzp1600_gpio_irq_set_type(struct irq_data *d, u32 type)
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{
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struct blzp1600_gpio *chip = get_blzp1600_gpio_from_irq_data(d);
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u32 edge_level, single_both, fall_rise;
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int mask = BIT(d->hwirq);
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guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock);
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edge_level = blzp1600_gpio_read(chip, GPIO_IS_REG);
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single_both = blzp1600_gpio_read(chip, GPIO_IBE_REG);
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fall_rise = blzp1600_gpio_read(chip, GPIO_IEV_REG);
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switch (type) {
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case IRQ_TYPE_EDGE_BOTH:
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edge_level &= ~mask;
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single_both |= mask;
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break;
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case IRQ_TYPE_EDGE_RISING:
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edge_level &= ~mask;
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single_both &= ~mask;
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fall_rise |= mask;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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edge_level &= ~mask;
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single_both &= ~mask;
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fall_rise &= ~mask;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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edge_level |= mask;
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fall_rise |= mask;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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edge_level |= mask;
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fall_rise &= ~mask;
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break;
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default:
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return -EINVAL;
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}
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blzp1600_gpio_write(chip, GPIO_IS_REG, edge_level);
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blzp1600_gpio_write(chip, GPIO_IBE_REG, single_both);
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blzp1600_gpio_write(chip, GPIO_IEV_REG, fall_rise);
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if (type & IRQ_TYPE_LEVEL_MASK)
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irq_set_handler_locked(d, handle_level_irq);
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else
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irq_set_handler_locked(d, handle_edge_irq);
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return 0;
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}
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static const struct irq_chip blzp1600_gpio_irqchip = {
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.name = DRIVER_NAME,
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.irq_ack = blzp1600_gpio_irq_ack,
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.irq_mask = blzp1600_gpio_irq_mask,
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.irq_unmask = blzp1600_gpio_irq_unmask,
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.irq_set_type = blzp1600_gpio_irq_set_type,
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.irq_enable = blzp1600_gpio_irq_enable,
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.irq_disable = blzp1600_gpio_irq_disable,
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.flags = IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND,
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GPIOCHIP_IRQ_RESOURCE_HELPERS,
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};
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static void blzp1600_gpio_irqhandler(struct irq_desc *desc)
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{
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struct blzp1600_gpio *gpio = get_blzp1600_gpio_from_irq_desc(desc);
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struct irq_chip *irqchip = irq_desc_get_chip(desc);
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unsigned long irq_status;
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int hwirq = 0;
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chained_irq_enter(irqchip, desc);
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irq_status = blzp1600_gpio_read(gpio, GPIO_RIS_REG);
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for_each_set_bit(hwirq, &irq_status, gpio->gc.ngpio)
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generic_handle_domain_irq(gpio->gc.irq.domain, hwirq);
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chained_irq_exit(irqchip, desc);
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}
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static int blzp1600_gpio_set_debounce(struct gpio_chip *gc, unsigned int offset,
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unsigned int debounce)
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{
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struct blzp1600_gpio *chip = gpiochip_get_data(gc);
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guard(raw_spinlock_irqsave)(&chip->gc.bgpio_lock);
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blzp1600_gpio_rmw(chip->base + GPIO_DB_REG, BIT(offset), debounce);
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return 0;
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}
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static int blzp1600_gpio_set_config(struct gpio_chip *gc, unsigned int offset, unsigned long config)
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{
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u32 debounce;
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if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
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return -ENOTSUPP;
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debounce = pinconf_to_config_argument(config);
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return blzp1600_gpio_set_debounce(gc, offset, debounce);
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}
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static int blzp1600_gpio_probe(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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struct blzp1600_gpio *chip;
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struct gpio_chip *gc;
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int ret;
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chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
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if (!chip)
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return -ENOMEM;
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chip->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(chip->base))
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return PTR_ERR(chip->base);
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ret = bgpio_init(&chip->gc, &pdev->dev, 4, chip->base + GPIO_IDATA_REG,
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chip->base + GPIO_SET_REG, chip->base + GPIO_CLR_REG,
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chip->base + GPIO_DIR_REG, NULL, 0);
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if (ret)
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return dev_err_probe(&pdev->dev, ret, "Failed to register generic gpio\n");
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/* configure the gpio chip */
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gc = &chip->gc;
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gc->set_config = blzp1600_gpio_set_config;
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if (of_property_read_bool(node, "interrupt-controller")) {
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struct gpio_irq_chip *girq;
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chip->irq = platform_get_irq(pdev, 0);
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if (chip->irq < 0)
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return chip->irq;
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girq = &gc->irq;
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gpio_irq_chip_set_chip(girq, &blzp1600_gpio_irqchip);
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girq->parent_handler = blzp1600_gpio_irqhandler;
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girq->num_parents = 1;
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girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents), GFP_KERNEL);
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if (!girq->parents)
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return -ENOMEM;
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girq->parents[0] = chip->irq;
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girq->default_type = IRQ_TYPE_NONE;
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}
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return devm_gpiochip_add_data(&pdev->dev, gc, chip);
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}
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static const struct of_device_id blzp1600_gpio_of_match[] = {
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{ .compatible = "blaize,blzp1600-gpio", },
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{ /* Sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, blzp1600_gpio_of_match);
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static struct platform_driver blzp1600_gpio_driver = {
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.driver = {
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.name = DRIVER_NAME,
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.of_match_table = of_match_ptr(blzp1600_gpio_of_match),
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},
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.probe = blzp1600_gpio_probe,
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};
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module_platform_driver(blzp1600_gpio_driver);
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MODULE_AUTHOR("Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>");
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MODULE_DESCRIPTION("Blaize BLZP1600 GPIO driver");
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MODULE_LICENSE("GPL");
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