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drm/amdgpu: Add pci replay count to nbio v7.9
Add implementation to get pcie replay count for nbio v7.9. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -32,6 +32,9 @@
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#define NPS_MODE_MASK 0x000000FFL
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#define NPS_MODE_MASK 0x000000FFL
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/* Core 0 Port 0 counter */
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#define smnPCIEP_NAK_COUNTER 0x1A340218
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static void nbio_v7_9_remap_hdp_registers(struct amdgpu_device *adev)
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static void nbio_v7_9_remap_hdp_registers(struct amdgpu_device *adev)
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{
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{
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WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
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WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
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@ -427,6 +430,22 @@ static void nbio_v7_9_init_registers(struct amdgpu_device *adev)
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}
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}
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}
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}
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static u64 nbio_v7_9_get_pcie_replay_count(struct amdgpu_device *adev)
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{
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u32 val, nak_r, nak_g;
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if (adev->flags & AMD_IS_APU)
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return 0;
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/* Get the number of NAKs received and generated */
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val = RREG32_PCIE(smnPCIEP_NAK_COUNTER);
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nak_r = val & 0xFFFF;
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nak_g = val >> 16;
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/* Add the total number of NAKs, i.e the number of replays */
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return (nak_r + nak_g);
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}
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const struct amdgpu_nbio_funcs nbio_v7_9_funcs = {
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const struct amdgpu_nbio_funcs nbio_v7_9_funcs = {
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.get_hdp_flush_req_offset = nbio_v7_9_get_hdp_flush_req_offset,
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.get_hdp_flush_req_offset = nbio_v7_9_get_hdp_flush_req_offset,
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.get_hdp_flush_done_offset = nbio_v7_9_get_hdp_flush_done_offset,
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.get_hdp_flush_done_offset = nbio_v7_9_get_hdp_flush_done_offset,
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@ -450,4 +469,5 @@ const struct amdgpu_nbio_funcs nbio_v7_9_funcs = {
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.get_compute_partition_mode = nbio_v7_9_get_compute_partition_mode,
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.get_compute_partition_mode = nbio_v7_9_get_compute_partition_mode,
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.get_memory_partition_mode = nbio_v7_9_get_memory_partition_mode,
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.get_memory_partition_mode = nbio_v7_9_get_memory_partition_mode,
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.init_registers = nbio_v7_9_init_registers,
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.init_registers = nbio_v7_9_init_registers,
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.get_pcie_replay_count = nbio_v7_9_get_pcie_replay_count,
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};
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};
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@ -895,7 +895,7 @@ static const struct amdgpu_asic_funcs aqua_vanjaram_asic_funcs =
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.init_doorbell_index = &aqua_vanjaram_doorbell_index_init,
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.init_doorbell_index = &aqua_vanjaram_doorbell_index_init,
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.get_pcie_usage = &vega20_get_pcie_usage,
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.get_pcie_usage = &vega20_get_pcie_usage,
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.need_reset_on_init = &soc15_need_reset_on_init,
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.need_reset_on_init = &soc15_need_reset_on_init,
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.get_pcie_replay_count = &soc15_get_pcie_replay_count,
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.get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count,
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.supports_baco = &soc15_supports_baco,
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.supports_baco = &soc15_supports_baco,
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.pre_asic_init = &soc15_pre_asic_init,
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.pre_asic_init = &soc15_pre_asic_init,
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.query_video_codecs = &soc15_query_video_codecs,
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.query_video_codecs = &soc15_query_video_codecs,
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