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drm/amdgpu/gfx_9.4.3: wait for reset done before remap
There is a racing condition that cp firmware modifies MQD in reset sequence after driver updates it for remapping. We have to wait till CP_HQD_ACTIVE becoming false then remap the queue. v2: fix KIQ locking (Alex) v3: fix KIQ locking harder Acked-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by: Jiadong Zhu <Jiadong.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -3433,7 +3433,7 @@ static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring,
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struct amdgpu_kiq *kiq = &adev->gfx.kiq[ring->xcc_id];
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struct amdgpu_kiq *kiq = &adev->gfx.kiq[ring->xcc_id];
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struct amdgpu_ring *kiq_ring = &kiq->ring;
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struct amdgpu_ring *kiq_ring = &kiq->ring;
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unsigned long flags;
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unsigned long flags;
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int r;
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int r, i;
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if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
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if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
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return -EINVAL;
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return -EINVAL;
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@ -3455,9 +3455,28 @@ static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring,
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if (r)
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if (r)
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return r;
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return r;
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/* make sure dequeue is complete*/
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gfx_v9_4_3_xcc_set_safe_mode(adev, ring->xcc_id);
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mutex_lock(&adev->srbm_mutex);
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soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, ring->xcc_id));
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for (i = 0; i < adev->usec_timeout; i++) {
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if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
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break;
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udelay(1);
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}
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if (i >= adev->usec_timeout)
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r = -ETIMEDOUT;
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soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, ring->xcc_id));
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mutex_unlock(&adev->srbm_mutex);
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gfx_v9_4_3_xcc_unset_safe_mode(adev, ring->xcc_id);
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if (r) {
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dev_err(adev->dev, "fail to wait on hqd deactive\n");
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return r;
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}
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r = amdgpu_bo_reserve(ring->mqd_obj, false);
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r = amdgpu_bo_reserve(ring->mqd_obj, false);
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if (unlikely(r != 0)){
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if (unlikely(r != 0)){
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DRM_ERROR("fail to resv mqd_obj\n");
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dev_err(adev->dev, "fail to resv mqd_obj\n");
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return r;
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return r;
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}
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}
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r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
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r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
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@ -3467,15 +3486,23 @@ static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring,
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ring->mqd_ptr = NULL;
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ring->mqd_ptr = NULL;
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}
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}
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amdgpu_bo_unreserve(ring->mqd_obj);
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amdgpu_bo_unreserve(ring->mqd_obj);
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if (r){
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if (r) {
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DRM_ERROR("fail to unresv mqd_obj\n");
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dev_err(adev->dev, "fail to unresv mqd_obj\n");
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return r;
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return r;
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}
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}
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spin_lock_irqsave(&kiq->ring_lock, flags);
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r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size);
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r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size);
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if (r) {
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spin_unlock_irqrestore(&kiq->ring_lock, flags);
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return -ENOMEM;
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}
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kiq->pmf->kiq_map_queues(kiq_ring, ring);
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kiq->pmf->kiq_map_queues(kiq_ring, ring);
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amdgpu_ring_commit(kiq_ring);
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spin_unlock_irqrestore(&kiq->ring_lock, flags);
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r = amdgpu_ring_test_ring(kiq_ring);
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r = amdgpu_ring_test_ring(kiq_ring);
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if (r){
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if (r) {
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DRM_ERROR("fail to remap queue\n");
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dev_err(adev->dev, "fail to remap queue\n");
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return r;
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return r;
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}
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}
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return amdgpu_ring_test_ring(ring);
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return amdgpu_ring_test_ring(ring);
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