mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-10-31 18:24:13 +00:00
dc0d5c1e5c
Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
632 lines
20 KiB
C
632 lines
20 KiB
C
/*
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* R8A66597 HCD (Host Controller Driver)
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*
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* Copyright (C) 2006-2007 Renesas Solutions Corp.
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* Portions Copyright (C) 2004 Psion Teklogix (for NetBook PRO)
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* Portions Copyright (C) 2004-2005 David Brownell
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* Portions Copyright (C) 1999 Roman Weissgaerber
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*
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* Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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#ifndef __R8A66597_H__
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#define __R8A66597_H__
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#define SYSCFG0 0x00
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#define SYSCFG1 0x02
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#define SYSSTS0 0x04
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#define SYSSTS1 0x06
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#define DVSTCTR0 0x08
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#define DVSTCTR1 0x0A
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#define TESTMODE 0x0C
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#define PINCFG 0x0E
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#define DMA0CFG 0x10
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#define DMA1CFG 0x12
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#define CFIFO 0x14
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#define D0FIFO 0x18
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#define D1FIFO 0x1C
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#define CFIFOSEL 0x20
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#define CFIFOCTR 0x22
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#define CFIFOSIE 0x24
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#define D0FIFOSEL 0x28
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#define D0FIFOCTR 0x2A
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#define D1FIFOSEL 0x2C
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#define D1FIFOCTR 0x2E
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#define INTENB0 0x30
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#define INTENB1 0x32
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#define INTENB2 0x34
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#define BRDYENB 0x36
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#define NRDYENB 0x38
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#define BEMPENB 0x3A
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#define SOFCFG 0x3C
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#define INTSTS0 0x40
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#define INTSTS1 0x42
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#define INTSTS2 0x44
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#define BRDYSTS 0x46
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#define NRDYSTS 0x48
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#define BEMPSTS 0x4A
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#define FRMNUM 0x4C
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#define UFRMNUM 0x4E
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#define USBADDR 0x50
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#define USBREQ 0x54
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#define USBVAL 0x56
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#define USBINDX 0x58
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#define USBLENG 0x5A
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#define DCPCFG 0x5C
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#define DCPMAXP 0x5E
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#define DCPCTR 0x60
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#define PIPESEL 0x64
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#define PIPECFG 0x68
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#define PIPEBUF 0x6A
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#define PIPEMAXP 0x6C
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#define PIPEPERI 0x6E
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#define PIPE1CTR 0x70
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#define PIPE2CTR 0x72
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#define PIPE3CTR 0x74
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#define PIPE4CTR 0x76
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#define PIPE5CTR 0x78
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#define PIPE6CTR 0x7A
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#define PIPE7CTR 0x7C
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#define PIPE8CTR 0x7E
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#define PIPE9CTR 0x80
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#define PIPE1TRE 0x90
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#define PIPE1TRN 0x92
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#define PIPE2TRE 0x94
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#define PIPE2TRN 0x96
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#define PIPE3TRE 0x98
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#define PIPE3TRN 0x9A
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#define PIPE4TRE 0x9C
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#define PIPE4TRN 0x9E
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#define PIPE5TRE 0xA0
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#define PIPE5TRN 0xA2
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#define DEVADD0 0xD0
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#define DEVADD1 0xD2
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#define DEVADD2 0xD4
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#define DEVADD3 0xD6
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#define DEVADD4 0xD8
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#define DEVADD5 0xDA
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#define DEVADD6 0xDC
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#define DEVADD7 0xDE
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#define DEVADD8 0xE0
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#define DEVADD9 0xE2
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#define DEVADDA 0xE4
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/* System Configuration Control Register */
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#define XTAL 0xC000 /* b15-14: Crystal selection */
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#define XTAL48 0x8000 /* 48MHz */
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#define XTAL24 0x4000 /* 24MHz */
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#define XTAL12 0x0000 /* 12MHz */
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#define XCKE 0x2000 /* b13: External clock enable */
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#define PLLC 0x0800 /* b11: PLL control */
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#define SCKE 0x0400 /* b10: USB clock enable */
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#define PCSDIS 0x0200 /* b9: not CS wakeup */
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#define LPSME 0x0100 /* b8: Low power sleep mode */
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#define HSE 0x0080 /* b7: Hi-speed enable */
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#define DCFM 0x0040 /* b6: Controller function select */
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#define DRPD 0x0020 /* b5: D+/- pull down control */
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#define DPRPU 0x0010 /* b4: D+ pull up control */
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#define USBE 0x0001 /* b0: USB module operation enable */
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/* System Configuration Status Register */
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#define OVCBIT 0x8000 /* b15-14: Over-current bit */
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#define OVCMON 0xC000 /* b15-14: Over-current monitor */
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#define SOFEA 0x0020 /* b5: SOF monitor */
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#define IDMON 0x0004 /* b3: ID-pin monitor */
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#define LNST 0x0003 /* b1-0: D+, D- line status */
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#define SE1 0x0003 /* SE1 */
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#define FS_KSTS 0x0002 /* Full-Speed K State */
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#define FS_JSTS 0x0001 /* Full-Speed J State */
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#define LS_JSTS 0x0002 /* Low-Speed J State */
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#define LS_KSTS 0x0001 /* Low-Speed K State */
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#define SE0 0x0000 /* SE0 */
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/* Device State Control Register */
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#define EXTLP0 0x0400 /* b10: External port */
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#define VBOUT 0x0200 /* b9: VBUS output */
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#define WKUP 0x0100 /* b8: Remote wakeup */
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#define RWUPE 0x0080 /* b7: Remote wakeup sense */
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#define USBRST 0x0040 /* b6: USB reset enable */
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#define RESUME 0x0020 /* b5: Resume enable */
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#define UACT 0x0010 /* b4: USB bus enable */
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#define RHST 0x0007 /* b1-0: Reset handshake status */
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#define HSPROC 0x0004 /* HS handshake is processing */
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#define HSMODE 0x0003 /* Hi-Speed mode */
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#define FSMODE 0x0002 /* Full-Speed mode */
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#define LSMODE 0x0001 /* Low-Speed mode */
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#define UNDECID 0x0000 /* Undecided */
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/* Test Mode Register */
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#define UTST 0x000F /* b3-0: Test select */
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#define H_TST_PACKET 0x000C /* HOST TEST Packet */
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#define H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */
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#define H_TST_K 0x000A /* HOST TEST K */
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#define H_TST_J 0x0009 /* HOST TEST J */
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#define H_TST_NORMAL 0x0000 /* HOST Normal Mode */
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#define P_TST_PACKET 0x0004 /* PERI TEST Packet */
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#define P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */
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#define P_TST_K 0x0002 /* PERI TEST K */
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#define P_TST_J 0x0001 /* PERI TEST J */
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#define P_TST_NORMAL 0x0000 /* PERI Normal Mode */
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/* Data Pin Configuration Register */
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#define LDRV 0x8000 /* b15: Drive Current Adjust */
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#define VIF1 0x0000 /* VIF = 1.8V */
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#define VIF3 0x8000 /* VIF = 3.3V */
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#define INTA 0x0001 /* b1: USB INT-pin active */
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/* DMAx Pin Configuration Register */
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#define DREQA 0x4000 /* b14: Dreq active select */
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#define BURST 0x2000 /* b13: Burst mode */
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#define DACKA 0x0400 /* b10: Dack active select */
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#define DFORM 0x0380 /* b9-7: DMA mode select */
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#define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
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#define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
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#define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */
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#define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */
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#define DENDA 0x0040 /* b6: Dend active select */
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#define PKTM 0x0020 /* b5: Packet mode */
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#define DENDE 0x0010 /* b4: Dend enable */
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#define OBUS 0x0004 /* b2: OUTbus mode */
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/* CFIFO/DxFIFO Port Select Register */
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#define RCNT 0x8000 /* b15: Read count mode */
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#define REW 0x4000 /* b14: Buffer rewind */
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#define DCLRM 0x2000 /* b13: DMA buffer clear mode */
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#define DREQE 0x1000 /* b12: DREQ output enable */
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#define MBW 0x0400 /* b10: Maximum bit width for FIFO access */
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#define MBW_8 0x0000 /* 8bit */
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#define MBW_16 0x0400 /* 16bit */
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#define BIGEND 0x0100 /* b8: Big endian mode */
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#define BYTE_LITTLE 0x0000 /* little dendian */
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#define BYTE_BIG 0x0100 /* big endifan */
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#define ISEL 0x0020 /* b5: DCP FIFO port direction select */
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#define CURPIPE 0x000F /* b2-0: PIPE select */
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/* CFIFO/DxFIFO Port Control Register */
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#define BVAL 0x8000 /* b15: Buffer valid flag */
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#define BCLR 0x4000 /* b14: Buffer clear */
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#define FRDY 0x2000 /* b13: FIFO ready */
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#define DTLN 0x0FFF /* b11-0: FIFO received data length */
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/* Interrupt Enable Register 0 */
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#define VBSE 0x8000 /* b15: VBUS interrupt */
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#define RSME 0x4000 /* b14: Resume interrupt */
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#define SOFE 0x2000 /* b13: Frame update interrupt */
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#define DVSE 0x1000 /* b12: Device state transition interrupt */
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#define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */
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#define BEMPE 0x0400 /* b10: Buffer empty interrupt */
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#define NRDYE 0x0200 /* b9: Buffer not ready interrupt */
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#define BRDYE 0x0100 /* b8: Buffer ready interrupt */
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/* Interrupt Enable Register 1 */
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#define OVRCRE 0x8000 /* b15: Over-current interrupt */
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#define BCHGE 0x4000 /* b14: USB us chenge interrupt */
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#define DTCHE 0x1000 /* b12: Detach sense interrupt */
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#define ATTCHE 0x0800 /* b11: Attach sense interrupt */
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#define EOFERRE 0x0040 /* b6: EOF error interrupt */
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#define SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */
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#define SACKE 0x0010 /* b4: SETUP ACK interrupt */
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/* BRDY Interrupt Enable/Status Register */
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#define BRDY9 0x0200 /* b9: PIPE9 */
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#define BRDY8 0x0100 /* b8: PIPE8 */
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#define BRDY7 0x0080 /* b7: PIPE7 */
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#define BRDY6 0x0040 /* b6: PIPE6 */
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#define BRDY5 0x0020 /* b5: PIPE5 */
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#define BRDY4 0x0010 /* b4: PIPE4 */
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#define BRDY3 0x0008 /* b3: PIPE3 */
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#define BRDY2 0x0004 /* b2: PIPE2 */
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#define BRDY1 0x0002 /* b1: PIPE1 */
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#define BRDY0 0x0001 /* b1: PIPE0 */
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/* NRDY Interrupt Enable/Status Register */
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#define NRDY9 0x0200 /* b9: PIPE9 */
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#define NRDY8 0x0100 /* b8: PIPE8 */
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#define NRDY7 0x0080 /* b7: PIPE7 */
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#define NRDY6 0x0040 /* b6: PIPE6 */
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#define NRDY5 0x0020 /* b5: PIPE5 */
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#define NRDY4 0x0010 /* b4: PIPE4 */
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#define NRDY3 0x0008 /* b3: PIPE3 */
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#define NRDY2 0x0004 /* b2: PIPE2 */
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#define NRDY1 0x0002 /* b1: PIPE1 */
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#define NRDY0 0x0001 /* b1: PIPE0 */
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/* BEMP Interrupt Enable/Status Register */
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#define BEMP9 0x0200 /* b9: PIPE9 */
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#define BEMP8 0x0100 /* b8: PIPE8 */
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#define BEMP7 0x0080 /* b7: PIPE7 */
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#define BEMP6 0x0040 /* b6: PIPE6 */
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#define BEMP5 0x0020 /* b5: PIPE5 */
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#define BEMP4 0x0010 /* b4: PIPE4 */
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#define BEMP3 0x0008 /* b3: PIPE3 */
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#define BEMP2 0x0004 /* b2: PIPE2 */
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#define BEMP1 0x0002 /* b1: PIPE1 */
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#define BEMP0 0x0001 /* b0: PIPE0 */
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/* SOF Pin Configuration Register */
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#define TRNENSEL 0x0100 /* b8: Select transaction enable period */
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#define BRDYM 0x0040 /* b6: BRDY clear timing */
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#define INTL 0x0020 /* b5: Interrupt sense select */
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#define EDGESTS 0x0010 /* b4: */
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#define SOFMODE 0x000C /* b3-2: SOF pin select */
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#define SOF_125US 0x0008 /* SOF OUT 125us Frame Signal */
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#define SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */
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#define SOF_DISABLE 0x0000 /* SOF OUT Disable */
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/* Interrupt Status Register 0 */
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#define VBINT 0x8000 /* b15: VBUS interrupt */
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#define RESM 0x4000 /* b14: Resume interrupt */
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#define SOFR 0x2000 /* b13: SOF frame update interrupt */
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#define DVST 0x1000 /* b12: Device state transition interrupt */
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#define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */
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#define BEMP 0x0400 /* b10: Buffer empty interrupt */
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#define NRDY 0x0200 /* b9: Buffer not ready interrupt */
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#define BRDY 0x0100 /* b8: Buffer ready interrupt */
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#define VBSTS 0x0080 /* b7: VBUS input port */
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#define DVSQ 0x0070 /* b6-4: Device state */
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#define DS_SPD_CNFG 0x0070 /* Suspend Configured */
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#define DS_SPD_ADDR 0x0060 /* Suspend Address */
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#define DS_SPD_DFLT 0x0050 /* Suspend Default */
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#define DS_SPD_POWR 0x0040 /* Suspend Powered */
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#define DS_SUSP 0x0040 /* Suspend */
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#define DS_CNFG 0x0030 /* Configured */
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#define DS_ADDS 0x0020 /* Address */
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#define DS_DFLT 0x0010 /* Default */
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#define DS_POWR 0x0000 /* Powered */
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#define DVSQS 0x0030 /* b5-4: Device state */
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#define VALID 0x0008 /* b3: Setup packet detected flag */
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#define CTSQ 0x0007 /* b2-0: Control transfer stage */
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#define CS_SQER 0x0006 /* Sequence error */
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#define CS_WRND 0x0005 /* Control write nodata status stage */
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#define CS_WRSS 0x0004 /* Control write status stage */
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#define CS_WRDS 0x0003 /* Control write data stage */
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#define CS_RDSS 0x0002 /* Control read status stage */
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#define CS_RDDS 0x0001 /* Control read data stage */
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#define CS_IDST 0x0000 /* Idle or setup stage */
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/* Interrupt Status Register 1 */
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#define OVRCR 0x8000 /* b15: Over-current interrupt */
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#define BCHG 0x4000 /* b14: USB bus chenge interrupt */
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#define DTCH 0x1000 /* b12: Detach sense interrupt */
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#define ATTCH 0x0800 /* b11: Attach sense interrupt */
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#define EOFERR 0x0040 /* b6: EOF-error interrupt */
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#define SIGN 0x0020 /* b5: Setup ignore interrupt */
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#define SACK 0x0010 /* b4: Setup acknowledge interrupt */
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/* Frame Number Register */
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#define OVRN 0x8000 /* b15: Overrun error */
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#define CRCE 0x4000 /* b14: Received data error */
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#define FRNM 0x07FF /* b10-0: Frame number */
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/* Micro Frame Number Register */
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#define UFRNM 0x0007 /* b2-0: Micro frame number */
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/* Default Control Pipe Maxpacket Size Register */
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/* Pipe Maxpacket Size Register */
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#define DEVSEL 0xF000 /* b15-14: Device address select */
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#define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */
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/* Default Control Pipe Control Register */
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#define BSTS 0x8000 /* b15: Buffer status */
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#define SUREQ 0x4000 /* b14: Send USB request */
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#define CSCLR 0x2000 /* b13: complete-split status clear */
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#define CSSTS 0x1000 /* b12: complete-split status */
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#define SUREQCLR 0x0800 /* b11: stop setup request */
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#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
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#define SQSET 0x0080 /* b7: Sequence toggle bit set */
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#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
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#define PBUSY 0x0020 /* b5: pipe busy */
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#define PINGE 0x0010 /* b4: ping enable */
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#define CCPL 0x0004 /* b2: Enable control transfer complete */
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#define PID 0x0003 /* b1-0: Response PID */
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#define PID_STALL11 0x0003 /* STALL */
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#define PID_STALL 0x0002 /* STALL */
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#define PID_BUF 0x0001 /* BUF */
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#define PID_NAK 0x0000 /* NAK */
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/* Pipe Window Select Register */
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#define PIPENM 0x0007 /* b2-0: Pipe select */
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/* Pipe Configuration Register */
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#define R8A66597_TYP 0xC000 /* b15-14: Transfer type */
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#define R8A66597_ISO 0xC000 /* Isochronous */
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#define R8A66597_INT 0x8000 /* Interrupt */
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#define R8A66597_BULK 0x4000 /* Bulk */
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#define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */
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#define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */
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#define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */
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#define R8A66597_SHTNAK 0x0080 /* b7: Transfer end NAK */
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#define R8A66597_DIR 0x0010 /* b4: Transfer direction select */
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#define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */
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/* Pipe Buffer Configuration Register */
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#define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
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#define BUFNMB 0x007F /* b6-0: Pipe buffer number */
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#define PIPE0BUF 256
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#define PIPExBUF 64
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/* Pipe Maxpacket Size Register */
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#define MXPS 0x07FF /* b10-0: Maxpacket size */
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/* Pipe Cycle Configuration Register */
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#define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */
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#define IITV 0x0007 /* b2-0: Isochronous interval */
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/* Pipex Control Register */
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#define BSTS 0x8000 /* b15: Buffer status */
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#define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */
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#define CSCLR 0x2000 /* b13: complete-split status clear */
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#define CSSTS 0x1000 /* b12: complete-split status */
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#define ATREPM 0x0400 /* b10: Auto repeat mode */
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#define ACLRM 0x0200 /* b9: Out buffer auto clear mode */
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#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
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#define SQSET 0x0080 /* b7: Sequence toggle bit set */
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#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
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#define PBUSY 0x0020 /* b5: pipe busy */
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#define PID 0x0003 /* b1-0: Response PID */
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/* PIPExTRE */
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#define TRENB 0x0200 /* b9: Transaction counter enable */
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#define TRCLR 0x0100 /* b8: Transaction counter clear */
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/* PIPExTRN */
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#define TRNCNT 0xFFFF /* b15-0: Transaction counter */
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/* DEVADDx */
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#define UPPHUB 0x7800
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#define HUBPORT 0x0700
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#define USBSPD 0x00C0
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#define RTPORT 0x0001
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#define R8A66597_MAX_NUM_PIPE 10
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#define R8A66597_BUF_BSIZE 8
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#define R8A66597_MAX_DEVICE 10
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#define R8A66597_MAX_ROOT_HUB 2
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#define R8A66597_MAX_SAMPLING 10
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#define R8A66597_MAX_DMA_CHANNEL 2
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#define R8A66597_PIPE_NO_DMA R8A66597_MAX_DMA_CHANNEL
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#define check_bulk_or_isoc(pipenum) ((pipenum >= 1 && pipenum <= 5))
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#define check_interrupt(pipenum) ((pipenum >= 6 && pipenum <= 9))
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#define make_devsel(addr) (addr << 12)
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struct r8a66597_pipe_info {
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u16 pipenum;
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u16 address; /* R8A66597 HCD usb address */
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u16 epnum;
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u16 maxpacket;
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u16 type;
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u16 bufnum;
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u16 buf_bsize;
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u16 interval;
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u16 dir_in;
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};
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struct r8a66597_pipe {
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struct r8a66597_pipe_info info;
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unsigned long fifoaddr;
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unsigned long fifosel;
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unsigned long fifoctr;
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unsigned long pipectr;
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unsigned long pipetre;
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unsigned long pipetrn;
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};
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struct r8a66597_td {
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struct r8a66597_pipe *pipe;
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struct urb *urb;
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struct list_head queue;
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u16 type;
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u16 pipenum;
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int iso_cnt;
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u16 address; /* R8A66597's USB address */
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u16 maxpacket;
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unsigned zero_packet:1;
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unsigned short_packet:1;
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unsigned set_address:1;
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};
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struct r8a66597_device {
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u16 address; /* R8A66597's USB address */
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u16 hub_port;
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u16 root_port;
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unsigned short ep_in_toggle;
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unsigned short ep_out_toggle;
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unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
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unsigned char dma_map;
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enum usb_device_state state;
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struct usb_device *udev;
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int usb_address;
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struct list_head device_list;
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};
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struct r8a66597_root_hub {
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u32 port;
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u16 old_syssts;
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int scount;
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struct r8a66597_device *dev;
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};
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struct r8a66597 {
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spinlock_t lock;
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unsigned long reg;
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struct r8a66597_device device0;
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struct r8a66597_root_hub root_hub[R8A66597_MAX_ROOT_HUB];
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struct list_head pipe_queue[R8A66597_MAX_NUM_PIPE];
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struct timer_list rh_timer;
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struct timer_list td_timer[R8A66597_MAX_NUM_PIPE];
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unsigned short address_map;
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unsigned short timeout_map;
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unsigned char pipe_cnt[R8A66597_MAX_NUM_PIPE];
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unsigned char dma_map;
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struct list_head child_device;
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unsigned long child_connect_map[4];
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};
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static inline struct r8a66597 *hcd_to_r8a66597(struct usb_hcd *hcd)
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{
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return (struct r8a66597 *)(hcd->hcd_priv);
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}
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static inline struct usb_hcd *r8a66597_to_hcd(struct r8a66597 *r8a66597)
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{
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return container_of((void *)r8a66597, struct usb_hcd, hcd_priv);
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}
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static inline struct r8a66597_td *r8a66597_get_td(struct r8a66597 *r8a66597,
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u16 pipenum)
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{
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if (unlikely(list_empty(&r8a66597->pipe_queue[pipenum])))
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return NULL;
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return list_entry(r8a66597->pipe_queue[pipenum].next,
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struct r8a66597_td, queue);
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}
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static inline struct urb *r8a66597_get_urb(struct r8a66597 *r8a66597,
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u16 pipenum)
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{
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struct r8a66597_td *td;
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td = r8a66597_get_td(r8a66597, pipenum);
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return (td ? td->urb : NULL);
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}
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static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
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{
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return inw(r8a66597->reg + offset);
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}
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static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
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unsigned long offset, u16 *buf,
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int len)
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{
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len = (len + 1) / 2;
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insw(r8a66597->reg + offset, buf, len);
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}
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static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
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unsigned long offset)
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{
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outw(val, r8a66597->reg + offset);
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}
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static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
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unsigned long offset, u16 *buf,
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int len)
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{
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unsigned long fifoaddr = r8a66597->reg + offset;
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int odd = len & 0x0001;
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len = len / 2;
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outsw(fifoaddr, buf, len);
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if (unlikely(odd)) {
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buf = &buf[len];
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outb((unsigned char)*buf, fifoaddr);
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}
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}
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static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
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u16 val, u16 pat, unsigned long offset)
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{
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u16 tmp;
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tmp = r8a66597_read(r8a66597, offset);
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tmp = tmp & (~pat);
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tmp = tmp | val;
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r8a66597_write(r8a66597, tmp, offset);
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}
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#define r8a66597_bclr(r8a66597, val, offset) \
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r8a66597_mdfy(r8a66597, 0, val, offset)
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#define r8a66597_bset(r8a66597, val, offset) \
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r8a66597_mdfy(r8a66597, val, 0, offset)
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static inline unsigned long get_syscfg_reg(int port)
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{
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return port == 0 ? SYSCFG0 : SYSCFG1;
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}
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static inline unsigned long get_syssts_reg(int port)
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{
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return port == 0 ? SYSSTS0 : SYSSTS1;
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}
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static inline unsigned long get_dvstctr_reg(int port)
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{
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return port == 0 ? DVSTCTR0 : DVSTCTR1;
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}
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static inline unsigned long get_intenb_reg(int port)
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{
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return port == 0 ? INTENB1 : INTENB2;
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}
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static inline unsigned long get_intsts_reg(int port)
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{
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return port == 0 ? INTSTS1 : INTSTS2;
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}
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static inline u16 get_rh_usb_speed(struct r8a66597 *r8a66597, int port)
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{
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unsigned long dvstctr_reg = get_dvstctr_reg(port);
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return r8a66597_read(r8a66597, dvstctr_reg) & RHST;
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}
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static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port,
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int power)
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{
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unsigned long dvstctr_reg = get_dvstctr_reg(port);
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if (power)
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r8a66597_bset(r8a66597, VBOUT, dvstctr_reg);
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else
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r8a66597_bclr(r8a66597, VBOUT, dvstctr_reg);
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}
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#define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2)
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#define get_pipetre_addr(pipenum) (PIPE1TRE + (pipenum - 1) * 4)
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#define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4)
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#define get_devadd_addr(address) (DEVADD0 + address * 2)
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#define enable_irq_ready(r8a66597, pipenum) \
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enable_pipe_irq(r8a66597, pipenum, BRDYENB)
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#define disable_irq_ready(r8a66597, pipenum) \
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disable_pipe_irq(r8a66597, pipenum, BRDYENB)
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#define enable_irq_empty(r8a66597, pipenum) \
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enable_pipe_irq(r8a66597, pipenum, BEMPENB)
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#define disable_irq_empty(r8a66597, pipenum) \
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disable_pipe_irq(r8a66597, pipenum, BEMPENB)
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#define enable_irq_nrdy(r8a66597, pipenum) \
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enable_pipe_irq(r8a66597, pipenum, NRDYENB)
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#define disable_irq_nrdy(r8a66597, pipenum) \
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disable_pipe_irq(r8a66597, pipenum, NRDYENB)
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#endif /* __R8A66597_H__ */
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