mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-10-31 18:24:13 +00:00
9e55e44e39
There are 2 headers: arch/x86/include/asm/mce.h arch/x86/kernel/cpu/mcheck/mce.h and in the latter small header: #include <asm/mce.h> This patch move all contents in the latter header into the former, and fix all files using the latter to include the former instead. Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
117 lines
2.7 KiB
C
117 lines
2.7 KiB
C
/*
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* Athlon specific Machine Check Exception Reporting
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* (C) Copyright 2002 Dave Jones <davej@redhat.com>
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*/
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/mce.h>
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#include <asm/msr.h>
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/* Machine Check Handler For AMD Athlon/Duron: */
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static void k7_machine_check(struct pt_regs *regs, long error_code)
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{
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u32 alow, ahigh, high, low;
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u32 mcgstl, mcgsth;
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int recover = 1;
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int i;
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rdmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
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if (mcgstl & (1<<0)) /* Recoverable ? */
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recover = 0;
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printk(KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n",
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smp_processor_id(), mcgsth, mcgstl);
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for (i = 1; i < nr_mce_banks; i++) {
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rdmsr(MSR_IA32_MC0_STATUS+i*4, low, high);
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if (high & (1<<31)) {
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char misc[20];
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char addr[24];
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misc[0] = '\0';
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addr[0] = '\0';
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if (high & (1<<29))
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recover |= 1;
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if (high & (1<<25))
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recover |= 2;
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high &= ~(1<<31);
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if (high & (1<<27)) {
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rdmsr(MSR_IA32_MC0_MISC+i*4, alow, ahigh);
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snprintf(misc, 20, "[%08x%08x]", ahigh, alow);
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}
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if (high & (1<<26)) {
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rdmsr(MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
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snprintf(addr, 24, " at %08x%08x", ahigh, alow);
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}
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printk(KERN_EMERG "CPU %d: Bank %d: %08x%08x%s%s\n",
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smp_processor_id(), i, high, low, misc, addr);
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/* Clear it: */
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wrmsr(MSR_IA32_MC0_STATUS+i*4, 0UL, 0UL);
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/* Serialize: */
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wmb();
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add_taint(TAINT_MACHINE_CHECK);
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}
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}
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if (recover & 2)
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panic("CPU context corrupt");
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if (recover & 1)
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panic("Unable to continue");
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printk(KERN_EMERG "Attempting to continue.\n");
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mcgstl &= ~(1<<2);
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wrmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
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}
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/* AMD K7 machine check is Intel like: */
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void amd_mcheck_init(struct cpuinfo_x86 *c)
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{
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u32 l, h;
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int i;
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if (!cpu_has(c, X86_FEATURE_MCE))
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return;
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machine_check_vector = k7_machine_check;
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/* Make sure the vector pointer is visible before we enable MCEs: */
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wmb();
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printk(KERN_INFO "Intel machine check architecture supported.\n");
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rdmsr(MSR_IA32_MCG_CAP, l, h);
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if (l & (1<<8)) /* Control register present ? */
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wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
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nr_mce_banks = l & 0xff;
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/*
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* Clear status for MC index 0 separately, we don't touch CTL,
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* as some K7 Athlons cause spurious MCEs when its enabled:
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*/
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if (boot_cpu_data.x86 == 6) {
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wrmsr(MSR_IA32_MC0_STATUS, 0x0, 0x0);
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i = 1;
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} else
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i = 0;
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for (; i < nr_mce_banks; i++) {
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wrmsr(MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
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wrmsr(MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
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}
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set_in_cr4(X86_CR4_MCE);
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printk(KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",
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smp_processor_id());
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}
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