mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-10-31 12:39:23 +00:00
380 lines
11 KiB
C
380 lines
11 KiB
C
/*
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* interrupts.c: Interrupt mappings for PNX833X.
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*
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* Copyright 2008 NXP Semiconductors
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* Chris Steel <chris.steel@nxp.com>
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* Daniel Laird <daniel.j.laird@nxp.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include <linux/hardirq.h>
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#include <linux/interrupt.h>
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#include <asm/mipsregs.h>
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#include <asm/irq_cpu.h>
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#include <irq.h>
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#include <irq-mapping.h>
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#include <gpio.h>
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static int mips_cpu_timer_irq;
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static const unsigned int irq_prio[PNX833X_PIC_NUM_IRQ] =
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{
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0, /* unused */
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4, /* PNX833X_PIC_I2C0_INT 1 */
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4, /* PNX833X_PIC_I2C1_INT 2 */
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1, /* PNX833X_PIC_UART0_INT 3 */
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1, /* PNX833X_PIC_UART1_INT 4 */
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6, /* PNX833X_PIC_TS_IN0_DV_INT 5 */
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6, /* PNX833X_PIC_TS_IN0_DMA_INT 6 */
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7, /* PNX833X_PIC_GPIO_INT 7 */
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4, /* PNX833X_PIC_AUDIO_DEC_INT 8 */
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5, /* PNX833X_PIC_VIDEO_DEC_INT 9 */
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4, /* PNX833X_PIC_CONFIG_INT 10 */
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4, /* PNX833X_PIC_AOI_INT 11 */
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9, /* PNX833X_PIC_SYNC_INT 12 */
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9, /* PNX8335_PIC_SATA_INT 13 */
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4, /* PNX833X_PIC_OSD_INT 14 */
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9, /* PNX833X_PIC_DISP1_INT 15 */
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4, /* PNX833X_PIC_DEINTERLACER_INT 16 */
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9, /* PNX833X_PIC_DISPLAY2_INT 17 */
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4, /* PNX833X_PIC_VC_INT 18 */
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4, /* PNX833X_PIC_SC_INT 19 */
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9, /* PNX833X_PIC_IDE_INT 20 */
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9, /* PNX833X_PIC_IDE_DMA_INT 21 */
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6, /* PNX833X_PIC_TS_IN1_DV_INT 22 */
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6, /* PNX833X_PIC_TS_IN1_DMA_INT 23 */
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4, /* PNX833X_PIC_SGDX_DMA_INT 24 */
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4, /* PNX833X_PIC_TS_OUT_INT 25 */
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4, /* PNX833X_PIC_IR_INT 26 */
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3, /* PNX833X_PIC_VMSP1_INT 27 */
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3, /* PNX833X_PIC_VMSP2_INT 28 */
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4, /* PNX833X_PIC_PIBC_INT 29 */
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4, /* PNX833X_PIC_TS_IN0_TRD_INT 30 */
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4, /* PNX833X_PIC_SGDX_TPD_INT 31 */
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5, /* PNX833X_PIC_USB_INT 32 */
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4, /* PNX833X_PIC_TS_IN1_TRD_INT 33 */
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4, /* PNX833X_PIC_CLOCK_INT 34 */
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4, /* PNX833X_PIC_SGDX_PARSER_INT 35 */
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4, /* PNX833X_PIC_VMSP_DMA_INT 36 */
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#if defined(CONFIG_SOC_PNX8335)
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4, /* PNX8335_PIC_MIU_INT 37 */
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4, /* PNX8335_PIC_AVCHIP_IRQ_INT 38 */
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9, /* PNX8335_PIC_SYNC_HD_INT 39 */
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9, /* PNX8335_PIC_DISP_HD_INT 40 */
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9, /* PNX8335_PIC_DISP_SCALER_INT 41 */
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4, /* PNX8335_PIC_OSD_HD1_INT 42 */
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4, /* PNX8335_PIC_DTL_WRITER_Y_INT 43 */
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4, /* PNX8335_PIC_DTL_WRITER_C_INT 44 */
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4, /* PNX8335_PIC_DTL_EMULATOR_Y_IR_INT 45 */
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4, /* PNX8335_PIC_DTL_EMULATOR_C_IR_INT 46 */
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4, /* PNX8335_PIC_DENC_TTX_INT 47 */
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4, /* PNX8335_PIC_MMI_SIF0_INT 48 */
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4, /* PNX8335_PIC_MMI_SIF1_INT 49 */
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4, /* PNX8335_PIC_MMI_CDMMU_INT 50 */
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4, /* PNX8335_PIC_PIBCS_INT 51 */
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12, /* PNX8335_PIC_ETHERNET_INT 52 */
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3, /* PNX8335_PIC_VMSP1_0_INT 53 */
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3, /* PNX8335_PIC_VMSP1_1_INT 54 */
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4, /* PNX8335_PIC_VMSP1_DMA_INT 55 */
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4, /* PNX8335_PIC_TDGR_DE_INT 56 */
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4, /* PNX8335_PIC_IR1_IRQ_INT 57 */
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#endif
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};
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static void pnx833x_timer_dispatch(void)
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{
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do_IRQ(mips_cpu_timer_irq);
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}
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static void pic_dispatch(void)
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{
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unsigned int irq = PNX833X_REGFIELD(PIC_INT_SRC, INT_SRC);
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if ((irq >= 1) && (irq < (PNX833X_PIC_NUM_IRQ))) {
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unsigned long priority = PNX833X_PIC_INT_PRIORITY;
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PNX833X_PIC_INT_PRIORITY = irq_prio[irq];
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if (irq == PNX833X_PIC_GPIO_INT) {
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unsigned long mask = PNX833X_PIO_INT_STATUS & PNX833X_PIO_INT_ENABLE;
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int pin;
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while ((pin = ffs(mask & 0xffff))) {
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pin -= 1;
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do_IRQ(PNX833X_GPIO_IRQ_BASE + pin);
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mask &= ~(1 << pin);
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}
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} else {
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do_IRQ(irq + PNX833X_PIC_IRQ_BASE);
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}
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PNX833X_PIC_INT_PRIORITY = priority;
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} else {
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printk(KERN_ERR "plat_irq_dispatch: unexpected irq %u\n", irq);
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}
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned int pending = read_c0_status() & read_c0_cause();
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if (pending & STATUSF_IP4)
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pic_dispatch();
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else if (pending & STATUSF_IP7)
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do_IRQ(PNX833X_TIMER_IRQ);
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else
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spurious_interrupt();
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}
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static inline void pnx833x_hard_enable_pic_irq(unsigned int irq)
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{
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/* Currently we do this by setting IRQ priority to 1.
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If priority support is being implemented, 1 should be repalced
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by a better value. */
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PNX833X_PIC_INT_REG(irq) = irq_prio[irq];
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}
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static inline void pnx833x_hard_disable_pic_irq(unsigned int irq)
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{
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/* Disable IRQ by writing setting it's priority to 0 */
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PNX833X_PIC_INT_REG(irq) = 0;
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}
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static int irqflags[PNX833X_PIC_NUM_IRQ]; /* initialized by zeroes */
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#define IRQFLAG_STARTED 1
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#define IRQFLAG_DISABLED 2
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static DEFINE_RAW_SPINLOCK(pnx833x_irq_lock);
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static unsigned int pnx833x_startup_pic_irq(unsigned int irq)
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{
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unsigned long flags;
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unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;
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raw_spin_lock_irqsave(&pnx833x_irq_lock, flags);
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irqflags[pic_irq] = IRQFLAG_STARTED; /* started, not disabled */
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pnx833x_hard_enable_pic_irq(pic_irq);
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raw_spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
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return 0;
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}
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static void pnx833x_shutdown_pic_irq(unsigned int irq)
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{
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unsigned long flags;
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unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;
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raw_spin_lock_irqsave(&pnx833x_irq_lock, flags);
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irqflags[pic_irq] = 0; /* not started */
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pnx833x_hard_disable_pic_irq(pic_irq);
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raw_spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
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}
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static void pnx833x_enable_pic_irq(unsigned int irq)
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{
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unsigned long flags;
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unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;
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raw_spin_lock_irqsave(&pnx833x_irq_lock, flags);
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irqflags[pic_irq] &= ~IRQFLAG_DISABLED;
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if (irqflags[pic_irq] == IRQFLAG_STARTED)
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pnx833x_hard_enable_pic_irq(pic_irq);
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raw_spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
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}
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static void pnx833x_disable_pic_irq(unsigned int irq)
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{
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unsigned long flags;
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unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;
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raw_spin_lock_irqsave(&pnx833x_irq_lock, flags);
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irqflags[pic_irq] |= IRQFLAG_DISABLED;
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pnx833x_hard_disable_pic_irq(pic_irq);
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raw_spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
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}
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static void pnx833x_ack_pic_irq(unsigned int irq)
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{
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}
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static void pnx833x_end_pic_irq(unsigned int irq)
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{
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}
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static DEFINE_RAW_SPINLOCK(pnx833x_gpio_pnx833x_irq_lock);
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static unsigned int pnx833x_startup_gpio_irq(unsigned int irq)
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{
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int pin = irq - PNX833X_GPIO_IRQ_BASE;
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unsigned long flags;
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raw_spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
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pnx833x_gpio_enable_irq(pin);
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raw_spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
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return 0;
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}
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static void pnx833x_enable_gpio_irq(unsigned int irq)
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{
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int pin = irq - PNX833X_GPIO_IRQ_BASE;
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unsigned long flags;
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raw_spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
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pnx833x_gpio_enable_irq(pin);
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raw_spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
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}
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static void pnx833x_disable_gpio_irq(unsigned int irq)
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{
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int pin = irq - PNX833X_GPIO_IRQ_BASE;
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unsigned long flags;
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raw_spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
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pnx833x_gpio_disable_irq(pin);
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raw_spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
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}
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static void pnx833x_ack_gpio_irq(unsigned int irq)
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{
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}
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static void pnx833x_end_gpio_irq(unsigned int irq)
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{
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int pin = irq - PNX833X_GPIO_IRQ_BASE;
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unsigned long flags;
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raw_spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
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pnx833x_gpio_clear_irq(pin);
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raw_spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
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}
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static int pnx833x_set_type_gpio_irq(unsigned int irq, unsigned int flow_type)
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{
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int pin = irq - PNX833X_GPIO_IRQ_BASE;
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int gpio_mode;
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switch (flow_type) {
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case IRQ_TYPE_EDGE_RISING:
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gpio_mode = GPIO_INT_EDGE_RISING;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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gpio_mode = GPIO_INT_EDGE_FALLING;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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gpio_mode = GPIO_INT_EDGE_BOTH;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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gpio_mode = GPIO_INT_LEVEL_HIGH;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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gpio_mode = GPIO_INT_LEVEL_LOW;
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break;
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default:
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gpio_mode = GPIO_INT_NONE;
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break;
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}
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pnx833x_gpio_setup_irq(gpio_mode, pin);
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return 0;
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}
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static struct irq_chip pnx833x_pic_irq_type = {
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.name = "PNX-PIC",
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.startup = pnx833x_startup_pic_irq,
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.shutdown = pnx833x_shutdown_pic_irq,
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.enable = pnx833x_enable_pic_irq,
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.disable = pnx833x_disable_pic_irq,
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.ack = pnx833x_ack_pic_irq,
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.end = pnx833x_end_pic_irq
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};
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static struct irq_chip pnx833x_gpio_irq_type = {
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.name = "PNX-GPIO",
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.startup = pnx833x_startup_gpio_irq,
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.shutdown = pnx833x_disable_gpio_irq,
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.enable = pnx833x_enable_gpio_irq,
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.disable = pnx833x_disable_gpio_irq,
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.ack = pnx833x_ack_gpio_irq,
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.end = pnx833x_end_gpio_irq,
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.set_type = pnx833x_set_type_gpio_irq
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};
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void __init arch_init_irq(void)
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{
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unsigned int irq;
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/* setup standard internal cpu irqs */
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mips_cpu_irq_init();
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/* Set IRQ information in irq_desc */
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for (irq = PNX833X_PIC_IRQ_BASE; irq < (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ); irq++) {
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pnx833x_hard_disable_pic_irq(irq);
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set_irq_chip_and_handler(irq, &pnx833x_pic_irq_type, handle_simple_irq);
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}
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for (irq = PNX833X_GPIO_IRQ_BASE; irq < (PNX833X_GPIO_IRQ_BASE + PNX833X_GPIO_NUM_IRQ); irq++)
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set_irq_chip_and_handler(irq, &pnx833x_gpio_irq_type, handle_simple_irq);
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/* Set PIC priority limiter register to 0 */
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PNX833X_PIC_INT_PRIORITY = 0;
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/* Setup GPIO IRQ dispatching */
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pnx833x_startup_pic_irq(PNX833X_PIC_GPIO_INT);
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/* Enable PIC IRQs (HWIRQ2) */
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if (cpu_has_vint)
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set_vi_handler(4, pic_dispatch);
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write_c0_status(read_c0_status() | IE_IRQ2);
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}
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unsigned int __cpuinit get_c0_compare_int(void)
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{
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if (cpu_has_vint)
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set_vi_handler(cp0_compare_irq, pnx833x_timer_dispatch);
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mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
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return mips_cpu_timer_irq;
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}
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void __init plat_time_init(void)
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{
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/* calculate mips_hpt_frequency based on PNX833X_CLOCK_CPUCP_CTL reg */
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extern unsigned long mips_hpt_frequency;
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unsigned long reg = PNX833X_CLOCK_CPUCP_CTL;
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if (!(PNX833X_BIT(reg, CLOCK_CPUCP_CTL, EXIT_RESET))) {
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/* Functional clock is disabled so use crystal frequency */
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mips_hpt_frequency = 25;
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} else {
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#if defined(CONFIG_SOC_PNX8335)
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/* Functional clock is enabled, so get clock multiplier */
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mips_hpt_frequency = 90 + (10 * PNX8335_REGFIELD(CLOCK_PLL_CPU_CTL, FREQ));
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#else
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static const unsigned long int freq[4] = {240, 160, 120, 80};
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mips_hpt_frequency = freq[PNX833X_FIELD(reg, CLOCK_CPUCP_CTL, DIV_CLOCK)];
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#endif
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}
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printk(KERN_INFO "CPU clock is %ld MHz\n", mips_hpt_frequency);
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mips_hpt_frequency *= 500000;
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}
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