mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-10-31 03:13:59 +00:00
5588978882
On some stepping of SNB cpu, the first command to be parsed in BLT
command streamer should be MI_BATCHBUFFER_START otherwise the GPU
may hang.
(cherry picked from commit 8d19215be8)
Conflicts:
drivers/gpu/drm/i915/intel_ringbuffer.c
drivers/gpu/drm/i915/intel_ringbuffer.h
Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
Cc: stable@kernel.org
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
148 lines
4.3 KiB
C
148 lines
4.3 KiB
C
#ifndef _INTEL_RINGBUFFER_H_
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#define _INTEL_RINGBUFFER_H_
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struct intel_hw_status_page {
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void *page_addr;
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unsigned int gfx_addr;
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struct drm_gem_object *obj;
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};
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#define I915_READ_TAIL(ring) I915_READ(RING_TAIL(ring->mmio_base))
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#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL(ring->mmio_base), val)
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#define I915_READ_START(ring) I915_READ(RING_START(ring->mmio_base))
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#define I915_WRITE_START(ring, val) I915_WRITE(RING_START(ring->mmio_base), val)
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#define I915_READ_HEAD(ring) I915_READ(RING_HEAD(ring->mmio_base))
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#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD(ring->mmio_base), val)
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#define I915_READ_CTL(ring) I915_READ(RING_CTL(ring->mmio_base))
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#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL(ring->mmio_base), val)
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struct drm_i915_gem_execbuffer2;
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struct intel_ring_buffer {
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const char *name;
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enum intel_ring_id {
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RING_RENDER = 0x1,
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RING_BSD = 0x2,
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RING_BLT = 0x4,
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} id;
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u32 mmio_base;
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unsigned long size;
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void *virtual_start;
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struct drm_device *dev;
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struct drm_gem_object *gem_object;
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unsigned int head;
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unsigned int tail;
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int space;
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struct intel_hw_status_page status_page;
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u32 irq_gem_seqno; /* last seq seem at irq time */
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u32 waiting_gem_seqno;
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int user_irq_refcount;
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void (*user_irq_get)(struct drm_device *dev,
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struct intel_ring_buffer *ring);
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void (*user_irq_put)(struct drm_device *dev,
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struct intel_ring_buffer *ring);
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int (*init)(struct drm_device *dev,
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struct intel_ring_buffer *ring);
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void (*write_tail)(struct drm_device *dev,
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struct intel_ring_buffer *ring,
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u32 value);
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void (*flush)(struct drm_device *dev,
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struct intel_ring_buffer *ring,
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u32 invalidate_domains,
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u32 flush_domains);
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u32 (*add_request)(struct drm_device *dev,
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struct intel_ring_buffer *ring,
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u32 flush_domains);
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u32 (*get_seqno)(struct drm_device *dev,
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struct intel_ring_buffer *ring);
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int (*dispatch_gem_execbuffer)(struct drm_device *dev,
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struct intel_ring_buffer *ring,
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struct drm_i915_gem_execbuffer2 *exec,
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struct drm_clip_rect *cliprects,
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uint64_t exec_offset);
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void (*cleanup)(struct intel_ring_buffer *ring);
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/**
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* List of objects currently involved in rendering from the
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* ringbuffer.
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*
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* Includes buffers having the contents of their GPU caches
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* flushed, not necessarily primitives. last_rendering_seqno
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* represents when the rendering involved will be completed.
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*
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* A reference is held on the buffer while on this list.
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*/
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struct list_head active_list;
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/**
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* List of breadcrumbs associated with GPU requests currently
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* outstanding.
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*/
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struct list_head request_list;
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/**
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* List of objects currently pending a GPU write flush.
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*
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* All elements on this list will belong to either the
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* active_list or flushing_list, last_rendering_seqno can
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* be used to differentiate between the two elements.
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*/
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struct list_head gpu_write_list;
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/**
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* Do we have some not yet emitted requests outstanding?
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*/
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bool outstanding_lazy_request;
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wait_queue_head_t irq_queue;
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drm_local_map_t map;
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void *private;
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};
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static inline u32
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intel_read_status_page(struct intel_ring_buffer *ring,
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int reg)
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{
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u32 *regs = ring->status_page.page_addr;
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return regs[reg];
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}
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int intel_init_ring_buffer(struct drm_device *dev,
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struct intel_ring_buffer *ring);
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void intel_cleanup_ring_buffer(struct drm_device *dev,
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struct intel_ring_buffer *ring);
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int intel_wait_ring_buffer(struct drm_device *dev,
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struct intel_ring_buffer *ring, int n);
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void intel_ring_begin(struct drm_device *dev,
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struct intel_ring_buffer *ring, int n);
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static inline void intel_ring_emit(struct drm_device *dev,
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struct intel_ring_buffer *ring,
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unsigned int data)
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{
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unsigned int *virt = ring->virtual_start + ring->tail;
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*virt = data;
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ring->tail += 4;
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}
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void intel_ring_advance(struct drm_device *dev,
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struct intel_ring_buffer *ring);
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u32 intel_ring_get_seqno(struct drm_device *dev,
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struct intel_ring_buffer *ring);
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int intel_init_render_ring_buffer(struct drm_device *dev);
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int intel_init_bsd_ring_buffer(struct drm_device *dev);
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int intel_init_blt_ring_buffer(struct drm_device *dev);
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u32 intel_ring_get_active_head(struct drm_device *dev,
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struct intel_ring_buffer *ring);
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void intel_ring_setup_status_page(struct drm_device *dev,
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struct intel_ring_buffer *ring);
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#endif /* _INTEL_RINGBUFFER_H_ */
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