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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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8426e1f6af
Introduce an atomic_inc_not_zero operation. Make this a special case of atomic_add_unless because lockless pagecache actually wants atomic_inc_not_negativeone due to its offset refcount. Signed-off-by: Nick Piggin <npiggin@suse.de> Cc: "Paul E. McKenney" <paulmck@us.ibm.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
161 lines
3.5 KiB
C
161 lines
3.5 KiB
C
#ifndef __ARCH_M68K_ATOMIC__
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#define __ARCH_M68K_ATOMIC__
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#include <linux/config.h>
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#include <asm/system.h> /* local_irq_XXX() */
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/*
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* Atomic operations that C can't guarantee us. Useful for
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* resource counting etc..
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*/
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/*
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* We do not have SMP m68k systems, so we don't have to deal with that.
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*/
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typedef struct { int counter; } atomic_t;
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#define ATOMIC_INIT(i) { (i) }
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#define atomic_read(v) ((v)->counter)
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#define atomic_set(v, i) (((v)->counter) = i)
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static inline void atomic_add(int i, atomic_t *v)
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{
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__asm__ __volatile__("addl %1,%0" : "+m" (*v) : "id" (i));
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}
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static inline void atomic_sub(int i, atomic_t *v)
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{
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__asm__ __volatile__("subl %1,%0" : "+m" (*v) : "id" (i));
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}
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static inline void atomic_inc(atomic_t *v)
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{
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__asm__ __volatile__("addql #1,%0" : "+m" (*v));
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}
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static inline void atomic_dec(atomic_t *v)
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{
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__asm__ __volatile__("subql #1,%0" : "+m" (*v));
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}
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static inline int atomic_dec_and_test(atomic_t *v)
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{
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char c;
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__asm__ __volatile__("subql #1,%1; seq %0" : "=d" (c), "+m" (*v));
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return c != 0;
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}
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static inline int atomic_inc_and_test(atomic_t *v)
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{
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char c;
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__asm__ __volatile__("addql #1,%1; seq %0" : "=d" (c), "+m" (*v));
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return c != 0;
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}
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#ifdef CONFIG_RMW_INSNS
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static inline int atomic_add_return(int i, atomic_t *v)
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{
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int t, tmp;
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__asm__ __volatile__(
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"1: movel %2,%1\n"
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" addl %3,%1\n"
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" casl %2,%1,%0\n"
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" jne 1b"
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: "+m" (*v), "=&d" (t), "=&d" (tmp)
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: "g" (i), "2" (atomic_read(v)));
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return t;
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}
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static inline int atomic_sub_return(int i, atomic_t *v)
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{
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int t, tmp;
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__asm__ __volatile__(
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"1: movel %2,%1\n"
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" subl %3,%1\n"
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" casl %2,%1,%0\n"
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" jne 1b"
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: "+m" (*v), "=&d" (t), "=&d" (tmp)
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: "g" (i), "2" (atomic_read(v)));
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return t;
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}
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#else /* !CONFIG_RMW_INSNS */
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static inline int atomic_add_return(int i, atomic_t * v)
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{
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unsigned long flags;
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int t;
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local_irq_save(flags);
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t = atomic_read(v);
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t += i;
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atomic_set(v, t);
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local_irq_restore(flags);
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return t;
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}
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static inline int atomic_sub_return(int i, atomic_t * v)
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{
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unsigned long flags;
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int t;
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local_irq_save(flags);
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t = atomic_read(v);
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t -= i;
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atomic_set(v, t);
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local_irq_restore(flags);
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return t;
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}
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#endif /* !CONFIG_RMW_INSNS */
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#define atomic_dec_return(v) atomic_sub_return(1, (v))
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#define atomic_inc_return(v) atomic_add_return(1, (v))
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static inline int atomic_sub_and_test(int i, atomic_t *v)
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{
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char c;
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__asm__ __volatile__("subl %2,%1; seq %0" : "=d" (c), "+m" (*v): "g" (i));
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return c != 0;
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}
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static inline int atomic_add_negative(int i, atomic_t *v)
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{
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char c;
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__asm__ __volatile__("addl %2,%1; smi %0" : "=d" (c), "+m" (*v): "g" (i));
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return c != 0;
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}
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static inline void atomic_clear_mask(unsigned long mask, unsigned long *v)
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{
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__asm__ __volatile__("andl %1,%0" : "+m" (*v) : "id" (~(mask)));
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}
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static inline void atomic_set_mask(unsigned long mask, unsigned long *v)
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{
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__asm__ __volatile__("orl %1,%0" : "+m" (*v) : "id" (mask));
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}
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#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
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#define atomic_add_unless(v, a, u) \
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({ \
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int c, old; \
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c = atomic_read(v); \
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while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \
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c = old; \
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c != (u); \
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})
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#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
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/* Atomic operations are already serializing */
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#define smp_mb__before_atomic_dec() barrier()
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#define smp_mb__after_atomic_dec() barrier()
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#define smp_mb__before_atomic_inc() barrier()
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#define smp_mb__after_atomic_inc() barrier()
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#endif /* __ARCH_M68K_ATOMIC __ */
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