mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
262 lines
7.0 KiB
C
262 lines
7.0 KiB
C
#ifndef __ALPHA_MMU_CONTEXT_H
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#define __ALPHA_MMU_CONTEXT_H
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/*
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* get a new mmu context..
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*
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* Copyright (C) 1996, Linus Torvalds
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*/
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#include <linux/config.h>
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#include <asm/system.h>
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#include <asm/machvec.h>
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#include <asm/compiler.h>
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/*
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* Force a context reload. This is needed when we change the page
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* table pointer or when we update the ASN of the current process.
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*/
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/* Don't get into trouble with dueling __EXTERN_INLINEs. */
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#ifndef __EXTERN_INLINE
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#include <asm/io.h>
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#endif
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extern inline unsigned long
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__reload_thread(struct pcb_struct *pcb)
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{
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register unsigned long a0 __asm__("$16");
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register unsigned long v0 __asm__("$0");
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a0 = virt_to_phys(pcb);
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__asm__ __volatile__(
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"call_pal %2 #__reload_thread"
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: "=r"(v0), "=r"(a0)
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: "i"(PAL_swpctx), "r"(a0)
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: "$1", "$22", "$23", "$24", "$25");
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return v0;
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}
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/*
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* The maximum ASN's the processor supports. On the EV4 this is 63
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* but the PAL-code doesn't actually use this information. On the
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* EV5 this is 127, and EV6 has 255.
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*
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* On the EV4, the ASNs are more-or-less useless anyway, as they are
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* only used as an icache tag, not for TB entries. On the EV5 and EV6,
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* ASN's also validate the TB entries, and thus make a lot more sense.
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*
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* The EV4 ASN's don't even match the architecture manual, ugh. And
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* I quote: "If a processor implements address space numbers (ASNs),
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* and the old PTE has the Address Space Match (ASM) bit clear (ASNs
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* in use) and the Valid bit set, then entries can also effectively be
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* made coherent by assigning a new, unused ASN to the currently
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* running process and not reusing the previous ASN before calling the
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* appropriate PALcode routine to invalidate the translation buffer (TB)".
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*
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* In short, the EV4 has a "kind of" ASN capability, but it doesn't actually
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* work correctly and can thus not be used (explaining the lack of PAL-code
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* support).
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*/
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#define EV4_MAX_ASN 63
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#define EV5_MAX_ASN 127
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#define EV6_MAX_ASN 255
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#ifdef CONFIG_ALPHA_GENERIC
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# define MAX_ASN (alpha_mv.max_asn)
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#else
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# ifdef CONFIG_ALPHA_EV4
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# define MAX_ASN EV4_MAX_ASN
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# elif defined(CONFIG_ALPHA_EV5)
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# define MAX_ASN EV5_MAX_ASN
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# else
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# define MAX_ASN EV6_MAX_ASN
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# endif
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#endif
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/*
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* cpu_last_asn(processor):
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* 63 0
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* +-------------+----------------+--------------+
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* | asn version | this processor | hardware asn |
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* +-------------+----------------+--------------+
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*/
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#ifdef CONFIG_SMP
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#include <asm/smp.h>
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#define cpu_last_asn(cpuid) (cpu_data[cpuid].last_asn)
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#else
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extern unsigned long last_asn;
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#define cpu_last_asn(cpuid) last_asn
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#endif /* CONFIG_SMP */
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#define WIDTH_HARDWARE_ASN 8
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#define ASN_FIRST_VERSION (1UL << WIDTH_HARDWARE_ASN)
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#define HARDWARE_ASN_MASK ((1UL << WIDTH_HARDWARE_ASN) - 1)
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/*
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* NOTE! The way this is set up, the high bits of the "asn_cache" (and
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* the "mm->context") are the ASN _version_ code. A version of 0 is
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* always considered invalid, so to invalidate another process you only
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* need to do "p->mm->context = 0".
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*
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* If we need more ASN's than the processor has, we invalidate the old
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* user TLB's (tbiap()) and start a new ASN version. That will automatically
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* force a new asn for any other processes the next time they want to
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* run.
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*/
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#ifndef __EXTERN_INLINE
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#define __EXTERN_INLINE extern inline
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#define __MMU_EXTERN_INLINE
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#endif
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static inline unsigned long
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__get_new_mm_context(struct mm_struct *mm, long cpu)
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{
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unsigned long asn = cpu_last_asn(cpu);
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unsigned long next = asn + 1;
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if ((asn & HARDWARE_ASN_MASK) >= MAX_ASN) {
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tbiap();
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imb();
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next = (asn & ~HARDWARE_ASN_MASK) + ASN_FIRST_VERSION;
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}
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cpu_last_asn(cpu) = next;
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return next;
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}
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__EXTERN_INLINE void
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ev5_switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm,
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struct task_struct *next)
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{
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/* Check if our ASN is of an older version, and thus invalid. */
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unsigned long asn;
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unsigned long mmc;
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long cpu = smp_processor_id();
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#ifdef CONFIG_SMP
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cpu_data[cpu].asn_lock = 1;
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barrier();
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#endif
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asn = cpu_last_asn(cpu);
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mmc = next_mm->context[cpu];
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if ((mmc ^ asn) & ~HARDWARE_ASN_MASK) {
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mmc = __get_new_mm_context(next_mm, cpu);
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next_mm->context[cpu] = mmc;
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}
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#ifdef CONFIG_SMP
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else
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cpu_data[cpu].need_new_asn = 1;
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#endif
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/* Always update the PCB ASN. Another thread may have allocated
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a new mm->context (via flush_tlb_mm) without the ASN serial
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number wrapping. We have no way to detect when this is needed. */
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next->thread_info->pcb.asn = mmc & HARDWARE_ASN_MASK;
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}
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__EXTERN_INLINE void
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ev4_switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm,
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struct task_struct *next)
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{
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/* As described, ASN's are broken for TLB usage. But we can
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optimize for switching between threads -- if the mm is
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unchanged from current we needn't flush. */
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/* ??? May not be needed because EV4 PALcode recognizes that
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ASN's are broken and does a tbiap itself on swpctx, under
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the "Must set ASN or flush" rule. At least this is true
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for a 1992 SRM, reports Joseph Martin (jmartin@hlo.dec.com).
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I'm going to leave this here anyway, just to Be Sure. -- r~ */
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if (prev_mm != next_mm)
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tbiap();
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/* Do continue to allocate ASNs, because we can still use them
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to avoid flushing the icache. */
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ev5_switch_mm(prev_mm, next_mm, next);
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}
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extern void __load_new_mm_context(struct mm_struct *);
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#ifdef CONFIG_SMP
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#define check_mmu_context() \
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do { \
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int cpu = smp_processor_id(); \
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cpu_data[cpu].asn_lock = 0; \
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barrier(); \
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if (cpu_data[cpu].need_new_asn) { \
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struct mm_struct * mm = current->active_mm; \
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cpu_data[cpu].need_new_asn = 0; \
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if (!mm->context[cpu]) \
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__load_new_mm_context(mm); \
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} \
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} while(0)
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#else
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#define check_mmu_context() do { } while(0)
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#endif
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__EXTERN_INLINE void
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ev5_activate_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm)
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{
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__load_new_mm_context(next_mm);
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}
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__EXTERN_INLINE void
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ev4_activate_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm)
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{
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__load_new_mm_context(next_mm);
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tbiap();
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}
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#define deactivate_mm(tsk,mm) do { } while (0)
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#ifdef CONFIG_ALPHA_GENERIC
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# define switch_mm(a,b,c) alpha_mv.mv_switch_mm((a),(b),(c))
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# define activate_mm(x,y) alpha_mv.mv_activate_mm((x),(y))
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#else
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# ifdef CONFIG_ALPHA_EV4
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# define switch_mm(a,b,c) ev4_switch_mm((a),(b),(c))
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# define activate_mm(x,y) ev4_activate_mm((x),(y))
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# else
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# define switch_mm(a,b,c) ev5_switch_mm((a),(b),(c))
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# define activate_mm(x,y) ev5_activate_mm((x),(y))
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# endif
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#endif
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extern inline int
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init_new_context(struct task_struct *tsk, struct mm_struct *mm)
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{
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int i;
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for (i = 0; i < NR_CPUS; i++)
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if (cpu_online(i))
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mm->context[i] = 0;
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if (tsk != current)
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tsk->thread_info->pcb.ptbr
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= ((unsigned long)mm->pgd - IDENT_ADDR) >> PAGE_SHIFT;
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return 0;
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}
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extern inline void
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destroy_context(struct mm_struct *mm)
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{
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/* Nothing to do. */
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}
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static inline void
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enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
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{
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tsk->thread_info->pcb.ptbr
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= ((unsigned long)mm->pgd - IDENT_ADDR) >> PAGE_SHIFT;
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}
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#ifdef __MMU_EXTERN_INLINE
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#undef __EXTERN_INLINE
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#undef __MMU_EXTERN_INLINE
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#endif
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#endif /* __ALPHA_MMU_CONTEXT_H */
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