mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-10-30 14:15:43 +00:00
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
293 lines
6.9 KiB
C
293 lines
6.9 KiB
C
/*****************************************************************************/
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/*
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* cd1400.h -- cd1400 UART hardware info.
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*
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* Copyright (C) 1996-1998 Stallion Technologies
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* Copyright (C) 1994-1996 Greg Ungerer.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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/*****************************************************************************/
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#ifndef _CD1400_H
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#define _CD1400_H
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/*****************************************************************************/
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/*
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* Define the number of async ports per cd1400 uart chip.
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*/
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#define CD1400_PORTS 4
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/*
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* Define the cd1400 uarts internal FIFO sizes.
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*/
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#define CD1400_TXFIFOSIZE 12
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#define CD1400_RXFIFOSIZE 12
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/*
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* Local RX FIFO thresh hold level. Also define the RTS thresh hold
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* based on the RX thresh hold.
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*/
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#define FIFO_RXTHRESHOLD 6
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#define FIFO_RTSTHRESHOLD 7
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/*****************************************************************************/
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/*
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* Define the cd1400 register addresses. These are all the valid
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* registers with the cd1400. Some are global, some virtual, some
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* per port.
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*/
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#define GFRCR 0x40
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#define CAR 0x68
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#define GCR 0x4b
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#define SVRR 0x67
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#define RICR 0x44
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#define TICR 0x45
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#define MICR 0x46
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#define RIR 0x6b
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#define TIR 0x6a
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#define MIR 0x69
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#define PPR 0x7e
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#define RIVR 0x43
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#define TIVR 0x42
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#define MIVR 0x41
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#define TDR 0x63
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#define RDSR 0x62
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#define MISR 0x4c
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#define EOSRR 0x60
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#define LIVR 0x18
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#define CCR 0x05
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#define SRER 0x06
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#define COR1 0x08
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#define COR2 0x09
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#define COR3 0x0a
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#define COR4 0x1e
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#define COR5 0x1f
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#define CCSR 0x0b
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#define RDCR 0x0e
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#define SCHR1 0x1a
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#define SCHR2 0x1b
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#define SCHR3 0x1c
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#define SCHR4 0x1d
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#define SCRL 0x22
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#define SCRH 0x23
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#define LNC 0x24
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#define MCOR1 0x15
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#define MCOR2 0x16
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#define RTPR 0x21
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#define MSVR1 0x6c
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#define MSVR2 0x6d
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#define PSVR 0x6f
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#define RBPR 0x78
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#define RCOR 0x7c
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#define TBPR 0x72
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#define TCOR 0x76
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/*****************************************************************************/
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/*
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* Define the set of baud rate clock divisors.
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*/
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#define CD1400_CLK0 8
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#define CD1400_CLK1 32
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#define CD1400_CLK2 128
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#define CD1400_CLK3 512
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#define CD1400_CLK4 2048
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#define CD1400_NUMCLKS 5
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/*****************************************************************************/
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/*
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* Define the clock pre-scalar value to be a 5 ms clock. This should be
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* OK for now. It would probably be better to make it 10 ms, but we
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* can't fit that divisor into 8 bits!
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*/
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#define PPR_SCALAR 244
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/*****************************************************************************/
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/*
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* Define values used to set character size options.
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*/
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#define COR1_CHL5 0x00
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#define COR1_CHL6 0x01
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#define COR1_CHL7 0x02
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#define COR1_CHL8 0x03
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/*
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* Define values used to set the number of stop bits.
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*/
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#define COR1_STOP1 0x00
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#define COR1_STOP15 0x04
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#define COR1_STOP2 0x08
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/*
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* Define values used to set the parity scheme in use.
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*/
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#define COR1_PARNONE 0x00
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#define COR1_PARFORCE 0x20
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#define COR1_PARENB 0x40
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#define COR1_PARIGNORE 0x10
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#define COR1_PARODD 0x80
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#define COR1_PAREVEN 0x00
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#define COR2_IXM 0x80
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#define COR2_TXIBE 0x40
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#define COR2_ETC 0x20
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#define COR2_LLM 0x10
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#define COR2_RLM 0x08
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#define COR2_RTSAO 0x04
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#define COR2_CTSAE 0x02
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#define COR3_SCDRNG 0x80
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#define COR3_SCD34 0x40
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#define COR3_FCT 0x20
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#define COR3_SCD12 0x10
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/*
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* Define values used by COR4.
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*/
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#define COR4_BRKINT 0x08
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#define COR4_IGNBRK 0x18
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/*****************************************************************************/
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/*
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* Define the modem control register values.
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* Note that the actual hardware is a little different to the conventional
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* pin names on the cd1400.
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*/
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#define MSVR1_DTR 0x01
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#define MSVR1_DSR 0x10
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#define MSVR1_RI 0x20
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#define MSVR1_CTS 0x40
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#define MSVR1_DCD 0x80
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#define MSVR2_RTS 0x02
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#define MSVR2_DSR 0x10
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#define MSVR2_RI 0x20
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#define MSVR2_CTS 0x40
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#define MSVR2_DCD 0x80
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#define MCOR1_DCD 0x80
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#define MCOR1_CTS 0x40
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#define MCOR1_RI 0x20
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#define MCOR1_DSR 0x10
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#define MCOR2_DCD 0x80
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#define MCOR2_CTS 0x40
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#define MCOR2_RI 0x20
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#define MCOR2_DSR 0x10
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/*****************************************************************************/
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/*
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* Define the bits used with the service (interrupt) enable register.
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*/
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#define SRER_NNDT 0x01
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#define SRER_TXEMPTY 0x02
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#define SRER_TXDATA 0x04
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#define SRER_RXDATA 0x10
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#define SRER_MODEM 0x80
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/*****************************************************************************/
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/*
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* Define operational commands for the command register.
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*/
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#define CCR_RESET 0x80
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#define CCR_CORCHANGE 0x4e
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#define CCR_SENDCH 0x20
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#define CCR_CHANCTRL 0x10
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#define CCR_TXENABLE (CCR_CHANCTRL | 0x08)
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#define CCR_TXDISABLE (CCR_CHANCTRL | 0x04)
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#define CCR_RXENABLE (CCR_CHANCTRL | 0x02)
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#define CCR_RXDISABLE (CCR_CHANCTRL | 0x01)
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#define CCR_SENDSCHR1 (CCR_SENDCH | 0x01)
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#define CCR_SENDSCHR2 (CCR_SENDCH | 0x02)
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#define CCR_SENDSCHR3 (CCR_SENDCH | 0x03)
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#define CCR_SENDSCHR4 (CCR_SENDCH | 0x04)
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#define CCR_RESETCHAN (CCR_RESET | 0x00)
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#define CCR_RESETFULL (CCR_RESET | 0x01)
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#define CCR_TXFLUSHFIFO (CCR_RESET | 0x02)
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#define CCR_MAXWAIT 10000
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/*****************************************************************************/
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/*
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* Define the valid acknowledgement types (for hw ack cycle).
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*/
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#define ACK_TYPMASK 0x07
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#define ACK_TYPTX 0x02
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#define ACK_TYPMDM 0x01
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#define ACK_TYPRXGOOD 0x03
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#define ACK_TYPRXBAD 0x07
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#define SVRR_RX 0x01
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#define SVRR_TX 0x02
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#define SVRR_MDM 0x04
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#define ST_OVERRUN 0x01
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#define ST_FRAMING 0x02
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#define ST_PARITY 0x04
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#define ST_BREAK 0x08
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#define ST_SCHAR1 0x10
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#define ST_SCHAR2 0x20
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#define ST_SCHAR3 0x30
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#define ST_SCHAR4 0x40
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#define ST_RANGE 0x70
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#define ST_SCHARMASK 0x70
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#define ST_TIMEOUT 0x80
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#define MISR_DCD 0x80
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#define MISR_CTS 0x40
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#define MISR_RI 0x20
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#define MISR_DSR 0x10
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/*****************************************************************************/
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/*
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* Defines for the CCSR status register.
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*/
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#define CCSR_RXENABLED 0x80
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#define CCSR_RXFLOWON 0x40
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#define CCSR_RXFLOWOFF 0x20
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#define CCSR_TXENABLED 0x08
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#define CCSR_TXFLOWON 0x04
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#define CCSR_TXFLOWOFF 0x02
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/*****************************************************************************/
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/*
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* Define the embedded commands.
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*/
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#define ETC_CMD 0x00
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#define ETC_STARTBREAK 0x81
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#define ETC_DELAY 0x82
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#define ETC_STOPBREAK 0x83
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/*****************************************************************************/
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#endif
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