mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-10-31 02:59:34 +00:00
21cb987914
Signed-off-by: Vivek Natarajan <vnatarajan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
235 lines
6.7 KiB
C
235 lines
6.7 KiB
C
/*
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* Copyright (c) 2009 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "hw.h"
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enum ath_bt_mode {
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ATH_BT_COEX_MODE_LEGACY, /* legacy rx_clear mode */
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ATH_BT_COEX_MODE_UNSLOTTED, /* untimed/unslotted mode */
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ATH_BT_COEX_MODE_SLOTTED, /* slotted mode */
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ATH_BT_COEX_MODE_DISALBED, /* coexistence disabled */
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};
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struct ath_btcoex_config {
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u8 bt_time_extend;
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bool bt_txstate_extend;
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bool bt_txframe_extend;
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enum ath_bt_mode bt_mode; /* coexistence mode */
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bool bt_quiet_collision;
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bool bt_rxclear_polarity; /* invert rx_clear as WLAN_ACTIVE*/
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u8 bt_priority_time;
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u8 bt_first_slot_time;
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bool bt_hold_rx_clear;
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};
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static const u16 ath_subsysid_tbl[] = {
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AR9280_COEX2WIRE_SUBSYSID,
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AT9285_COEX3WIRE_SA_SUBSYSID,
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AT9285_COEX3WIRE_DA_SUBSYSID
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};
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/*
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* Checks the subsystem id of the device to see if it
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* supports btcoex
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*/
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bool ath9k_hw_btcoex_supported(struct ath_hw *ah)
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{
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int i;
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if (!ah->hw_version.subsysid)
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return false;
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for (i = 0; i < ARRAY_SIZE(ath_subsysid_tbl); i++)
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if (ah->hw_version.subsysid == ath_subsysid_tbl[i])
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return true;
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return false;
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}
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void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum)
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{
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struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
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const struct ath_btcoex_config ath_bt_config = {
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.bt_time_extend = 0,
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.bt_txstate_extend = true,
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.bt_txframe_extend = true,
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.bt_mode = ATH_BT_COEX_MODE_SLOTTED,
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.bt_quiet_collision = true,
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.bt_rxclear_polarity = true,
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.bt_priority_time = 2,
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.bt_first_slot_time = 5,
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.bt_hold_rx_clear = true,
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};
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u32 i;
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btcoex_hw->bt_coex_mode =
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(btcoex_hw->bt_coex_mode & AR_BT_QCU_THRESH) |
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SM(ath_bt_config.bt_time_extend, AR_BT_TIME_EXTEND) |
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SM(ath_bt_config.bt_txstate_extend, AR_BT_TXSTATE_EXTEND) |
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SM(ath_bt_config.bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) |
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SM(ath_bt_config.bt_mode, AR_BT_MODE) |
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SM(ath_bt_config.bt_quiet_collision, AR_BT_QUIET) |
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SM(ath_bt_config.bt_rxclear_polarity, AR_BT_RX_CLEAR_POLARITY) |
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SM(ath_bt_config.bt_priority_time, AR_BT_PRIORITY_TIME) |
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SM(ath_bt_config.bt_first_slot_time, AR_BT_FIRST_SLOT_TIME) |
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SM(qnum, AR_BT_QCU_THRESH);
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btcoex_hw->bt_coex_mode2 =
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SM(ath_bt_config.bt_hold_rx_clear, AR_BT_HOLD_RX_CLEAR) |
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SM(ATH_BTCOEX_BMISS_THRESH, AR_BT_BCN_MISS_THRESH) |
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AR_BT_DISABLE_BT_ANT;
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for (i = 0; i < 32; i++)
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ah->hw_gen_timers.gen_timer_index[(debruijn32 << i) >> 27] = i;
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}
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EXPORT_SYMBOL(ath9k_hw_init_btcoex_hw);
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void ath9k_hw_btcoex_init_2wire(struct ath_hw *ah)
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{
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struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
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/* connect bt_active to baseband */
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REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
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(AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
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AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
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REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
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AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
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/* Set input mux for bt_active to gpio pin */
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REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
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AR_GPIO_INPUT_MUX1_BT_ACTIVE,
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btcoex_hw->btactive_gpio);
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/* Configure the desired gpio port for input */
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ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio);
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}
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EXPORT_SYMBOL(ath9k_hw_btcoex_init_2wire);
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void ath9k_hw_btcoex_init_3wire(struct ath_hw *ah)
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{
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struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
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/* btcoex 3-wire */
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REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
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(AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB |
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AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB));
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/* Set input mux for bt_prority_async and
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* bt_active_async to GPIO pins */
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REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
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AR_GPIO_INPUT_MUX1_BT_ACTIVE,
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btcoex_hw->btactive_gpio);
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REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
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AR_GPIO_INPUT_MUX1_BT_PRIORITY,
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btcoex_hw->btpriority_gpio);
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/* Configure the desired GPIO ports for input */
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ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio);
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ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btpriority_gpio);
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}
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EXPORT_SYMBOL(ath9k_hw_btcoex_init_3wire);
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static void ath9k_hw_btcoex_enable_2wire(struct ath_hw *ah)
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{
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struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
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/* Configure the desired GPIO port for TX_FRAME output */
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ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
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AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
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}
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void ath9k_hw_btcoex_set_weight(struct ath_hw *ah,
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u32 bt_weight,
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u32 wlan_weight)
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{
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struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
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btcoex_hw->bt_coex_weights = SM(bt_weight, AR_BTCOEX_BT_WGHT) |
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SM(wlan_weight, AR_BTCOEX_WL_WGHT);
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}
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EXPORT_SYMBOL(ath9k_hw_btcoex_set_weight);
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static void ath9k_hw_btcoex_enable_3wire(struct ath_hw *ah)
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{
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struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
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u32 val;
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/*
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* Program coex mode and weight registers to
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* enable coex 3-wire
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*/
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REG_WRITE(ah, AR_BT_COEX_MODE, btcoex_hw->bt_coex_mode);
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REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex_hw->bt_coex_weights);
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REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex_hw->bt_coex_mode2);
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if (AR_SREV_9271(ah)) {
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val = REG_READ(ah, 0x50040);
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val &= 0xFFFFFEFF;
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REG_WRITE(ah, 0x50040, val);
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}
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REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
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REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
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ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
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AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL);
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}
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void ath9k_hw_btcoex_enable(struct ath_hw *ah)
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{
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struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
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switch (btcoex_hw->scheme) {
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case ATH_BTCOEX_CFG_NONE:
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break;
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case ATH_BTCOEX_CFG_2WIRE:
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ath9k_hw_btcoex_enable_2wire(ah);
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break;
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case ATH_BTCOEX_CFG_3WIRE:
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ath9k_hw_btcoex_enable_3wire(ah);
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break;
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}
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REG_RMW(ah, AR_GPIO_PDPU,
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(0x2 << (btcoex_hw->btactive_gpio * 2)),
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(0x3 << (btcoex_hw->btactive_gpio * 2)));
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ah->btcoex_hw.enabled = true;
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}
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EXPORT_SYMBOL(ath9k_hw_btcoex_enable);
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void ath9k_hw_btcoex_disable(struct ath_hw *ah)
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{
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struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
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ath9k_hw_set_gpio(ah, btcoex_hw->wlanactive_gpio, 0);
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ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio,
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AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
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if (btcoex_hw->scheme == ATH_BTCOEX_CFG_3WIRE) {
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REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE);
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REG_WRITE(ah, AR_BT_COEX_WEIGHT, 0);
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REG_WRITE(ah, AR_BT_COEX_MODE2, 0);
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}
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ah->btcoex_hw.enabled = false;
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}
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EXPORT_SYMBOL(ath9k_hw_btcoex_disable);
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