mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-10-31 03:13:59 +00:00
9094a086f2
The percal struct and bitmask for the initial DC calibration are not used anywhere, so they can be removed. Signed-off-by: Felix Fietkau <nbd@openwrt.org Signed-off-by: John W. Linville <linville@tuxdriver.com>
987 lines
29 KiB
C
987 lines
29 KiB
C
/*
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* Copyright (c) 2008-2010 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "hw.h"
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#include "hw-ops.h"
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#include "ar9002_phy.h"
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#define AR9285_CLCAL_REDO_THRESH 1
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static void ar9002_hw_setup_calibration(struct ath_hw *ah,
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struct ath9k_cal_list *currCal)
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{
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struct ath_common *common = ath9k_hw_common(ah);
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REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
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AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
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currCal->calData->calCountMax);
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switch (currCal->calData->calType) {
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case IQ_MISMATCH_CAL:
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REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
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ath_print(common, ATH_DBG_CALIBRATE,
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"starting IQ Mismatch Calibration\n");
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break;
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case ADC_GAIN_CAL:
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REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
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ath_print(common, ATH_DBG_CALIBRATE,
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"starting ADC Gain Calibration\n");
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break;
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case ADC_DC_CAL:
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REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
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ath_print(common, ATH_DBG_CALIBRATE,
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"starting ADC DC Calibration\n");
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break;
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case TEMP_COMP_CAL:
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break; /* Not supported */
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}
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REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
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AR_PHY_TIMING_CTRL4_DO_CAL);
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}
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static bool ar9002_hw_per_calibration(struct ath_hw *ah,
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struct ath9k_channel *ichan,
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u8 rxchainmask,
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struct ath9k_cal_list *currCal)
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{
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struct ath9k_hw_cal_data *caldata = ah->caldata;
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bool iscaldone = false;
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if (currCal->calState == CAL_RUNNING) {
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if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
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AR_PHY_TIMING_CTRL4_DO_CAL)) {
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currCal->calData->calCollect(ah);
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ah->cal_samples++;
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if (ah->cal_samples >=
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currCal->calData->calNumSamples) {
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int i, numChains = 0;
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for (i = 0; i < AR5416_MAX_CHAINS; i++) {
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if (rxchainmask & (1 << i))
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numChains++;
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}
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currCal->calData->calPostProc(ah, numChains);
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caldata->CalValid |= currCal->calData->calType;
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currCal->calState = CAL_DONE;
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iscaldone = true;
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} else {
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ar9002_hw_setup_calibration(ah, currCal);
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}
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}
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} else if (!(caldata->CalValid & currCal->calData->calType)) {
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ath9k_hw_reset_calibration(ah, currCal);
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}
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return iscaldone;
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}
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/* Assumes you are talking about the currently configured channel */
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static bool ar9002_hw_iscal_supported(struct ath_hw *ah,
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enum ath9k_cal_types calType)
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{
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struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
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switch (calType & ah->supp_cals) {
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case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
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return true;
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case ADC_GAIN_CAL:
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case ADC_DC_CAL:
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if (!(conf->channel->band == IEEE80211_BAND_2GHZ &&
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conf_is_ht20(conf)))
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return true;
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break;
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}
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return false;
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}
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static void ar9002_hw_iqcal_collect(struct ath_hw *ah)
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{
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int i;
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for (i = 0; i < AR5416_MAX_CHAINS; i++) {
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ah->totalPowerMeasI[i] +=
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REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
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ah->totalPowerMeasQ[i] +=
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REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
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ah->totalIqCorrMeas[i] +=
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(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
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ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
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"%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
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ah->cal_samples, i, ah->totalPowerMeasI[i],
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ah->totalPowerMeasQ[i],
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ah->totalIqCorrMeas[i]);
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}
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}
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static void ar9002_hw_adc_gaincal_collect(struct ath_hw *ah)
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{
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int i;
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for (i = 0; i < AR5416_MAX_CHAINS; i++) {
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ah->totalAdcIOddPhase[i] +=
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REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
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ah->totalAdcIEvenPhase[i] +=
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REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
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ah->totalAdcQOddPhase[i] +=
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REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
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ah->totalAdcQEvenPhase[i] +=
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REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
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ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
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"%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
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"oddq=0x%08x; evenq=0x%08x;\n",
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ah->cal_samples, i,
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ah->totalAdcIOddPhase[i],
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ah->totalAdcIEvenPhase[i],
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ah->totalAdcQOddPhase[i],
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ah->totalAdcQEvenPhase[i]);
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}
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}
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static void ar9002_hw_adc_dccal_collect(struct ath_hw *ah)
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{
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int i;
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for (i = 0; i < AR5416_MAX_CHAINS; i++) {
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ah->totalAdcDcOffsetIOddPhase[i] +=
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(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
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ah->totalAdcDcOffsetIEvenPhase[i] +=
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(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
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ah->totalAdcDcOffsetQOddPhase[i] +=
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(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
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ah->totalAdcDcOffsetQEvenPhase[i] +=
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(int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
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ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
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"%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
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"oddq=0x%08x; evenq=0x%08x;\n",
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ah->cal_samples, i,
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ah->totalAdcDcOffsetIOddPhase[i],
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ah->totalAdcDcOffsetIEvenPhase[i],
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ah->totalAdcDcOffsetQOddPhase[i],
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ah->totalAdcDcOffsetQEvenPhase[i]);
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}
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}
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static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
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{
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struct ath_common *common = ath9k_hw_common(ah);
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u32 powerMeasQ, powerMeasI, iqCorrMeas;
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u32 qCoffDenom, iCoffDenom;
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int32_t qCoff, iCoff;
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int iqCorrNeg, i;
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for (i = 0; i < numChains; i++) {
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powerMeasI = ah->totalPowerMeasI[i];
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powerMeasQ = ah->totalPowerMeasQ[i];
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iqCorrMeas = ah->totalIqCorrMeas[i];
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ath_print(common, ATH_DBG_CALIBRATE,
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"Starting IQ Cal and Correction for Chain %d\n",
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i);
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ath_print(common, ATH_DBG_CALIBRATE,
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"Orignal: Chn %diq_corr_meas = 0x%08x\n",
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i, ah->totalIqCorrMeas[i]);
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iqCorrNeg = 0;
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if (iqCorrMeas > 0x80000000) {
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iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
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iqCorrNeg = 1;
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}
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ath_print(common, ATH_DBG_CALIBRATE,
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"Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
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ath_print(common, ATH_DBG_CALIBRATE,
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"Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
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ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
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iqCorrNeg);
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iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
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qCoffDenom = powerMeasQ / 64;
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if ((powerMeasQ != 0) && (iCoffDenom != 0) &&
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(qCoffDenom != 0)) {
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iCoff = iqCorrMeas / iCoffDenom;
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qCoff = powerMeasI / qCoffDenom - 64;
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ath_print(common, ATH_DBG_CALIBRATE,
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"Chn %d iCoff = 0x%08x\n", i, iCoff);
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ath_print(common, ATH_DBG_CALIBRATE,
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"Chn %d qCoff = 0x%08x\n", i, qCoff);
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iCoff = iCoff & 0x3f;
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ath_print(common, ATH_DBG_CALIBRATE,
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"New: Chn %d iCoff = 0x%08x\n", i, iCoff);
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if (iqCorrNeg == 0x0)
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iCoff = 0x40 - iCoff;
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if (qCoff > 15)
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qCoff = 15;
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else if (qCoff <= -16)
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qCoff = -16;
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ath_print(common, ATH_DBG_CALIBRATE,
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"Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
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i, iCoff, qCoff);
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REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
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AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
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iCoff);
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REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
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AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
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qCoff);
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ath_print(common, ATH_DBG_CALIBRATE,
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"IQ Cal and Correction done for Chain %d\n",
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i);
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}
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}
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REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
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AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
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}
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static void ar9002_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
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{
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struct ath_common *common = ath9k_hw_common(ah);
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u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
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u32 qGainMismatch, iGainMismatch, val, i;
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for (i = 0; i < numChains; i++) {
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iOddMeasOffset = ah->totalAdcIOddPhase[i];
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iEvenMeasOffset = ah->totalAdcIEvenPhase[i];
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qOddMeasOffset = ah->totalAdcQOddPhase[i];
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qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
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ath_print(common, ATH_DBG_CALIBRATE,
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"Starting ADC Gain Cal for Chain %d\n", i);
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ath_print(common, ATH_DBG_CALIBRATE,
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"Chn %d pwr_meas_odd_i = 0x%08x\n", i,
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iOddMeasOffset);
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ath_print(common, ATH_DBG_CALIBRATE,
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"Chn %d pwr_meas_even_i = 0x%08x\n", i,
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iEvenMeasOffset);
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ath_print(common, ATH_DBG_CALIBRATE,
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"Chn %d pwr_meas_odd_q = 0x%08x\n", i,
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qOddMeasOffset);
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ath_print(common, ATH_DBG_CALIBRATE,
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"Chn %d pwr_meas_even_q = 0x%08x\n", i,
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qEvenMeasOffset);
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if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
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iGainMismatch =
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((iEvenMeasOffset * 32) /
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iOddMeasOffset) & 0x3f;
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qGainMismatch =
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((qOddMeasOffset * 32) /
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qEvenMeasOffset) & 0x3f;
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ath_print(common, ATH_DBG_CALIBRATE,
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"Chn %d gain_mismatch_i = 0x%08x\n", i,
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iGainMismatch);
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ath_print(common, ATH_DBG_CALIBRATE,
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"Chn %d gain_mismatch_q = 0x%08x\n", i,
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qGainMismatch);
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val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
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val &= 0xfffff000;
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val |= (qGainMismatch) | (iGainMismatch << 6);
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REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
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ath_print(common, ATH_DBG_CALIBRATE,
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"ADC Gain Cal done for Chain %d\n", i);
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}
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}
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REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
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REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
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AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
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}
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static void ar9002_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
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{
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struct ath_common *common = ath9k_hw_common(ah);
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u32 iOddMeasOffset, iEvenMeasOffset, val, i;
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int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
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const struct ath9k_percal_data *calData =
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ah->cal_list_curr->calData;
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u32 numSamples =
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(1 << (calData->calCountMax + 5)) * calData->calNumSamples;
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for (i = 0; i < numChains; i++) {
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iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i];
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iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i];
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qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
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qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
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ath_print(common, ATH_DBG_CALIBRATE,
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"Starting ADC DC Offset Cal for Chain %d\n", i);
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ath_print(common, ATH_DBG_CALIBRATE,
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"Chn %d pwr_meas_odd_i = %d\n", i,
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iOddMeasOffset);
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ath_print(common, ATH_DBG_CALIBRATE,
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"Chn %d pwr_meas_even_i = %d\n", i,
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iEvenMeasOffset);
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ath_print(common, ATH_DBG_CALIBRATE,
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"Chn %d pwr_meas_odd_q = %d\n", i,
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qOddMeasOffset);
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ath_print(common, ATH_DBG_CALIBRATE,
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"Chn %d pwr_meas_even_q = %d\n", i,
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qEvenMeasOffset);
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iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
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numSamples) & 0x1ff;
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qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
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numSamples) & 0x1ff;
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ath_print(common, ATH_DBG_CALIBRATE,
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"Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
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iDcMismatch);
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ath_print(common, ATH_DBG_CALIBRATE,
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"Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
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qDcMismatch);
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val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
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val &= 0xc0000fff;
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val |= (qDcMismatch << 12) | (iDcMismatch << 21);
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REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
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ath_print(common, ATH_DBG_CALIBRATE,
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"ADC DC Offset Cal done for Chain %d\n", i);
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}
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REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
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REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
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AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
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}
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static void ar9287_hw_olc_temp_compensation(struct ath_hw *ah)
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{
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u32 rddata;
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int32_t delta, currPDADC, slope;
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rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
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currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
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if (ah->initPDADC == 0 || currPDADC == 0) {
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/*
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* Zero value indicates that no frames have been transmitted
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* yet, can't do temperature compensation until frames are
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* transmitted.
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*/
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return;
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} else {
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slope = ah->eep_ops->get_eeprom(ah, EEP_TEMPSENSE_SLOPE);
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if (slope == 0) { /* to avoid divide by zero case */
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delta = 0;
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} else {
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delta = ((currPDADC - ah->initPDADC)*4) / slope;
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}
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REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11,
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AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
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REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11,
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AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
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}
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}
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static void ar9280_hw_olc_temp_compensation(struct ath_hw *ah)
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{
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u32 rddata, i;
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int delta, currPDADC, regval;
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rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
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currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
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if (ah->initPDADC == 0 || currPDADC == 0)
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return;
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if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G))
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delta = (currPDADC - ah->initPDADC + 4) / 8;
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|
else
|
|
delta = (currPDADC - ah->initPDADC + 5) / 10;
|
|
|
|
if (delta != ah->PDADCdelta) {
|
|
ah->PDADCdelta = delta;
|
|
for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
|
|
regval = ah->originalGain[i] - delta;
|
|
if (regval < 0)
|
|
regval = 0;
|
|
|
|
REG_RMW_FIELD(ah,
|
|
AR_PHY_TX_GAIN_TBL1 + i * 4,
|
|
AR_PHY_TX_GAIN, regval);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void ar9271_hw_pa_cal(struct ath_hw *ah, bool is_reset)
|
|
{
|
|
u32 regVal;
|
|
unsigned int i;
|
|
u32 regList[][2] = {
|
|
{ 0x786c, 0 },
|
|
{ 0x7854, 0 },
|
|
{ 0x7820, 0 },
|
|
{ 0x7824, 0 },
|
|
{ 0x7868, 0 },
|
|
{ 0x783c, 0 },
|
|
{ 0x7838, 0 } ,
|
|
{ 0x7828, 0 } ,
|
|
};
|
|
|
|
for (i = 0; i < ARRAY_SIZE(regList); i++)
|
|
regList[i][1] = REG_READ(ah, regList[i][0]);
|
|
|
|
regVal = REG_READ(ah, 0x7834);
|
|
regVal &= (~(0x1));
|
|
REG_WRITE(ah, 0x7834, regVal);
|
|
regVal = REG_READ(ah, 0x9808);
|
|
regVal |= (0x1 << 27);
|
|
REG_WRITE(ah, 0x9808, regVal);
|
|
|
|
/* 786c,b23,1, pwddac=1 */
|
|
REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
|
|
/* 7854, b5,1, pdrxtxbb=1 */
|
|
REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
|
|
/* 7854, b7,1, pdv2i=1 */
|
|
REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
|
|
/* 7854, b8,1, pddacinterface=1 */
|
|
REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
|
|
/* 7824,b12,0, offcal=0 */
|
|
REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
|
|
/* 7838, b1,0, pwddb=0 */
|
|
REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
|
|
/* 7820,b11,0, enpacal=0 */
|
|
REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
|
|
/* 7820,b25,1, pdpadrv1=0 */
|
|
REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
|
|
/* 7820,b24,0, pdpadrv2=0 */
|
|
REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
|
|
/* 7820,b23,0, pdpaout=0 */
|
|
REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
|
|
/* 783c,b14-16,7, padrvgn2tab_0=7 */
|
|
REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
|
|
/*
|
|
* 7838,b29-31,0, padrvgn1tab_0=0
|
|
* does not matter since we turn it off
|
|
*/
|
|
REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
|
|
|
|
REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9271_AN_RF2G3_CCOMP, 0xfff);
|
|
|
|
/* Set:
|
|
* localmode=1,bmode=1,bmoderxtx=1,synthon=1,
|
|
* txon=1,paon=1,oscon=1,synthon_force=1
|
|
*/
|
|
REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
|
|
udelay(30);
|
|
REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0);
|
|
|
|
/* find off_6_1; */
|
|
for (i = 6; i > 0; i--) {
|
|
regVal = REG_READ(ah, 0x7834);
|
|
regVal |= (1 << (20 + i));
|
|
REG_WRITE(ah, 0x7834, regVal);
|
|
udelay(1);
|
|
/* regVal = REG_READ(ah, 0x7834); */
|
|
regVal &= (~(0x1 << (20 + i)));
|
|
regVal |= (MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9)
|
|
<< (20 + i));
|
|
REG_WRITE(ah, 0x7834, regVal);
|
|
}
|
|
|
|
regVal = (regVal >> 20) & 0x7f;
|
|
|
|
/* Update PA cal info */
|
|
if ((!is_reset) && (ah->pacal_info.prev_offset == regVal)) {
|
|
if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
|
|
ah->pacal_info.max_skipcount =
|
|
2 * ah->pacal_info.max_skipcount;
|
|
ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
|
|
} else {
|
|
ah->pacal_info.max_skipcount = 1;
|
|
ah->pacal_info.skipcount = 0;
|
|
ah->pacal_info.prev_offset = regVal;
|
|
}
|
|
|
|
ENABLE_REGWRITE_BUFFER(ah);
|
|
|
|
regVal = REG_READ(ah, 0x7834);
|
|
regVal |= 0x1;
|
|
REG_WRITE(ah, 0x7834, regVal);
|
|
regVal = REG_READ(ah, 0x9808);
|
|
regVal &= (~(0x1 << 27));
|
|
REG_WRITE(ah, 0x9808, regVal);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(regList); i++)
|
|
REG_WRITE(ah, regList[i][0], regList[i][1]);
|
|
|
|
REGWRITE_BUFFER_FLUSH(ah);
|
|
DISABLE_REGWRITE_BUFFER(ah);
|
|
}
|
|
|
|
static inline void ar9285_hw_pa_cal(struct ath_hw *ah, bool is_reset)
|
|
{
|
|
struct ath_common *common = ath9k_hw_common(ah);
|
|
u32 regVal;
|
|
int i, offset, offs_6_1, offs_0;
|
|
u32 ccomp_org, reg_field;
|
|
u32 regList[][2] = {
|
|
{ 0x786c, 0 },
|
|
{ 0x7854, 0 },
|
|
{ 0x7820, 0 },
|
|
{ 0x7824, 0 },
|
|
{ 0x7868, 0 },
|
|
{ 0x783c, 0 },
|
|
{ 0x7838, 0 },
|
|
};
|
|
|
|
ath_print(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
|
|
|
|
/* PA CAL is not needed for high power solution */
|
|
if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
|
|
AR5416_EEP_TXGAIN_HIGH_POWER)
|
|
return;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(regList); i++)
|
|
regList[i][1] = REG_READ(ah, regList[i][0]);
|
|
|
|
regVal = REG_READ(ah, 0x7834);
|
|
regVal &= (~(0x1));
|
|
REG_WRITE(ah, 0x7834, regVal);
|
|
regVal = REG_READ(ah, 0x9808);
|
|
regVal |= (0x1 << 27);
|
|
REG_WRITE(ah, 0x9808, regVal);
|
|
|
|
REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
|
|
REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
|
|
REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
|
|
REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
|
|
REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
|
|
REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
|
|
REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
|
|
REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
|
|
REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
|
|
REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
|
|
REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
|
|
REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
|
|
ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
|
|
REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf);
|
|
|
|
REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
|
|
udelay(30);
|
|
REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);
|
|
REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);
|
|
|
|
for (i = 6; i > 0; i--) {
|
|
regVal = REG_READ(ah, 0x7834);
|
|
regVal |= (1 << (19 + i));
|
|
REG_WRITE(ah, 0x7834, regVal);
|
|
udelay(1);
|
|
regVal = REG_READ(ah, 0x7834);
|
|
regVal &= (~(0x1 << (19 + i)));
|
|
reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
|
|
regVal |= (reg_field << (19 + i));
|
|
REG_WRITE(ah, 0x7834, regVal);
|
|
}
|
|
|
|
REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);
|
|
udelay(1);
|
|
reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);
|
|
REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);
|
|
offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
|
|
offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);
|
|
|
|
offset = (offs_6_1<<1) | offs_0;
|
|
offset = offset - 0;
|
|
offs_6_1 = offset>>1;
|
|
offs_0 = offset & 1;
|
|
|
|
if ((!is_reset) && (ah->pacal_info.prev_offset == offset)) {
|
|
if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
|
|
ah->pacal_info.max_skipcount =
|
|
2 * ah->pacal_info.max_skipcount;
|
|
ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
|
|
} else {
|
|
ah->pacal_info.max_skipcount = 1;
|
|
ah->pacal_info.skipcount = 0;
|
|
ah->pacal_info.prev_offset = offset;
|
|
}
|
|
|
|
REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
|
|
REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
|
|
|
|
regVal = REG_READ(ah, 0x7834);
|
|
regVal |= 0x1;
|
|
REG_WRITE(ah, 0x7834, regVal);
|
|
regVal = REG_READ(ah, 0x9808);
|
|
regVal &= (~(0x1 << 27));
|
|
REG_WRITE(ah, 0x9808, regVal);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(regList); i++)
|
|
REG_WRITE(ah, regList[i][0], regList[i][1]);
|
|
|
|
REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
|
|
}
|
|
|
|
static void ar9002_hw_pa_cal(struct ath_hw *ah, bool is_reset)
|
|
{
|
|
if (AR_SREV_9271(ah)) {
|
|
if (is_reset || !ah->pacal_info.skipcount)
|
|
ar9271_hw_pa_cal(ah, is_reset);
|
|
else
|
|
ah->pacal_info.skipcount--;
|
|
} else if (AR_SREV_9285_12_OR_LATER(ah)) {
|
|
if (is_reset || !ah->pacal_info.skipcount)
|
|
ar9285_hw_pa_cal(ah, is_reset);
|
|
else
|
|
ah->pacal_info.skipcount--;
|
|
}
|
|
}
|
|
|
|
static void ar9002_hw_olc_temp_compensation(struct ath_hw *ah)
|
|
{
|
|
if (OLC_FOR_AR9287_10_LATER)
|
|
ar9287_hw_olc_temp_compensation(ah);
|
|
else if (OLC_FOR_AR9280_20_LATER)
|
|
ar9280_hw_olc_temp_compensation(ah);
|
|
}
|
|
|
|
static bool ar9002_hw_calibrate(struct ath_hw *ah,
|
|
struct ath9k_channel *chan,
|
|
u8 rxchainmask,
|
|
bool longcal)
|
|
{
|
|
bool iscaldone = true;
|
|
struct ath9k_cal_list *currCal = ah->cal_list_curr;
|
|
bool nfcal, nfcal_pending = false;
|
|
|
|
nfcal = !!(REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF);
|
|
if (ah->caldata)
|
|
nfcal_pending = ah->caldata->nfcal_pending;
|
|
|
|
if (currCal && !nfcal &&
|
|
(currCal->calState == CAL_RUNNING ||
|
|
currCal->calState == CAL_WAITING)) {
|
|
iscaldone = ar9002_hw_per_calibration(ah, chan,
|
|
rxchainmask, currCal);
|
|
if (iscaldone) {
|
|
ah->cal_list_curr = currCal = currCal->calNext;
|
|
|
|
if (currCal->calState == CAL_WAITING) {
|
|
iscaldone = false;
|
|
ath9k_hw_reset_calibration(ah, currCal);
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Do NF cal only at longer intervals */
|
|
if (longcal || nfcal_pending) {
|
|
/* Do periodic PAOffset Cal */
|
|
ar9002_hw_pa_cal(ah, false);
|
|
ar9002_hw_olc_temp_compensation(ah);
|
|
|
|
/*
|
|
* Get the value from the previous NF cal and update
|
|
* history buffer.
|
|
*/
|
|
if (ath9k_hw_getnf(ah, chan)) {
|
|
/*
|
|
* Load the NF from history buffer of the current
|
|
* channel.
|
|
* NF is slow time-variant, so it is OK to use a
|
|
* historical value.
|
|
*/
|
|
ath9k_hw_loadnf(ah, ah->curchan);
|
|
}
|
|
|
|
if (longcal)
|
|
ath9k_hw_start_nfcal(ah, false);
|
|
}
|
|
|
|
return iscaldone;
|
|
}
|
|
|
|
/* Carrier leakage Calibration fix */
|
|
static bool ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan)
|
|
{
|
|
struct ath_common *common = ath9k_hw_common(ah);
|
|
|
|
REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
|
|
if (IS_CHAN_HT20(chan)) {
|
|
REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
|
|
REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
|
|
REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
|
|
AR_PHY_AGC_CONTROL_FLTR_CAL);
|
|
REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
|
|
REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
|
|
if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
|
|
AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
|
|
ath_print(common, ATH_DBG_CALIBRATE, "offset "
|
|
"calibration failed to complete in "
|
|
"1ms; noisy ??\n");
|
|
return false;
|
|
}
|
|
REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
|
|
REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
|
|
REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
|
|
}
|
|
REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
|
|
REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
|
|
REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
|
|
REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
|
|
if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
|
|
0, AH_WAIT_TIMEOUT)) {
|
|
ath_print(common, ATH_DBG_CALIBRATE, "offset calibration "
|
|
"failed to complete in 1ms; noisy ??\n");
|
|
return false;
|
|
}
|
|
|
|
REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
|
|
REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
|
|
REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
|
|
|
|
return true;
|
|
}
|
|
|
|
static bool ar9285_hw_clc(struct ath_hw *ah, struct ath9k_channel *chan)
|
|
{
|
|
int i;
|
|
u_int32_t txgain_max;
|
|
u_int32_t clc_gain, gain_mask = 0, clc_num = 0;
|
|
u_int32_t reg_clc_I0, reg_clc_Q0;
|
|
u_int32_t i0_num = 0;
|
|
u_int32_t q0_num = 0;
|
|
u_int32_t total_num = 0;
|
|
u_int32_t reg_rf2g5_org;
|
|
bool retv = true;
|
|
|
|
if (!(ar9285_hw_cl_cal(ah, chan)))
|
|
return false;
|
|
|
|
txgain_max = MS(REG_READ(ah, AR_PHY_TX_PWRCTRL7),
|
|
AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX);
|
|
|
|
for (i = 0; i < (txgain_max+1); i++) {
|
|
clc_gain = (REG_READ(ah, (AR_PHY_TX_GAIN_TBL1+(i<<2))) &
|
|
AR_PHY_TX_GAIN_CLC) >> AR_PHY_TX_GAIN_CLC_S;
|
|
if (!(gain_mask & (1 << clc_gain))) {
|
|
gain_mask |= (1 << clc_gain);
|
|
clc_num++;
|
|
}
|
|
}
|
|
|
|
for (i = 0; i < clc_num; i++) {
|
|
reg_clc_I0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
|
|
& AR_PHY_CLC_I0) >> AR_PHY_CLC_I0_S;
|
|
reg_clc_Q0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
|
|
& AR_PHY_CLC_Q0) >> AR_PHY_CLC_Q0_S;
|
|
if (reg_clc_I0 == 0)
|
|
i0_num++;
|
|
|
|
if (reg_clc_Q0 == 0)
|
|
q0_num++;
|
|
}
|
|
total_num = i0_num + q0_num;
|
|
if (total_num > AR9285_CLCAL_REDO_THRESH) {
|
|
reg_rf2g5_org = REG_READ(ah, AR9285_RF2G5);
|
|
if (AR_SREV_9285E_20(ah)) {
|
|
REG_WRITE(ah, AR9285_RF2G5,
|
|
(reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
|
|
AR9285_RF2G5_IC50TX_XE_SET);
|
|
} else {
|
|
REG_WRITE(ah, AR9285_RF2G5,
|
|
(reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
|
|
AR9285_RF2G5_IC50TX_SET);
|
|
}
|
|
retv = ar9285_hw_cl_cal(ah, chan);
|
|
REG_WRITE(ah, AR9285_RF2G5, reg_rf2g5_org);
|
|
}
|
|
return retv;
|
|
}
|
|
|
|
static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
|
|
{
|
|
struct ath_common *common = ath9k_hw_common(ah);
|
|
|
|
if (AR_SREV_9271(ah) || AR_SREV_9285_12_OR_LATER(ah)) {
|
|
if (!ar9285_hw_clc(ah, chan))
|
|
return false;
|
|
} else {
|
|
if (AR_SREV_9280_20_OR_LATER(ah)) {
|
|
if (!AR_SREV_9287_11_OR_LATER(ah))
|
|
REG_CLR_BIT(ah, AR_PHY_ADC_CTL,
|
|
AR_PHY_ADC_CTL_OFF_PWDADC);
|
|
REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
|
|
AR_PHY_AGC_CONTROL_FLTR_CAL);
|
|
}
|
|
|
|
/* Calibrate the AGC */
|
|
REG_WRITE(ah, AR_PHY_AGC_CONTROL,
|
|
REG_READ(ah, AR_PHY_AGC_CONTROL) |
|
|
AR_PHY_AGC_CONTROL_CAL);
|
|
|
|
/* Poll for offset calibration complete */
|
|
if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
|
|
AR_PHY_AGC_CONTROL_CAL,
|
|
0, AH_WAIT_TIMEOUT)) {
|
|
ath_print(common, ATH_DBG_CALIBRATE,
|
|
"offset calibration failed to "
|
|
"complete in 1ms; noisy environment?\n");
|
|
return false;
|
|
}
|
|
|
|
if (AR_SREV_9280_20_OR_LATER(ah)) {
|
|
if (!AR_SREV_9287_11_OR_LATER(ah))
|
|
REG_SET_BIT(ah, AR_PHY_ADC_CTL,
|
|
AR_PHY_ADC_CTL_OFF_PWDADC);
|
|
REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
|
|
AR_PHY_AGC_CONTROL_FLTR_CAL);
|
|
}
|
|
}
|
|
|
|
/* Do PA Calibration */
|
|
ar9002_hw_pa_cal(ah, true);
|
|
|
|
/* Do NF Calibration after DC offset and other calibrations */
|
|
ath9k_hw_start_nfcal(ah, true);
|
|
|
|
if (ah->caldata)
|
|
ah->caldata->nfcal_pending = true;
|
|
|
|
ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
|
|
|
|
/* Enable IQ, ADC Gain and ADC DC offset CALs */
|
|
if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
|
|
if (ar9002_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
|
|
INIT_CAL(&ah->adcgain_caldata);
|
|
INSERT_CAL(ah, &ah->adcgain_caldata);
|
|
ath_print(common, ATH_DBG_CALIBRATE,
|
|
"enabling ADC Gain Calibration.\n");
|
|
}
|
|
if (ar9002_hw_iscal_supported(ah, ADC_DC_CAL)) {
|
|
INIT_CAL(&ah->adcdc_caldata);
|
|
INSERT_CAL(ah, &ah->adcdc_caldata);
|
|
ath_print(common, ATH_DBG_CALIBRATE,
|
|
"enabling ADC DC Calibration.\n");
|
|
}
|
|
if (ar9002_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
|
|
INIT_CAL(&ah->iq_caldata);
|
|
INSERT_CAL(ah, &ah->iq_caldata);
|
|
ath_print(common, ATH_DBG_CALIBRATE,
|
|
"enabling IQ Calibration.\n");
|
|
}
|
|
|
|
ah->cal_list_curr = ah->cal_list;
|
|
|
|
if (ah->cal_list_curr)
|
|
ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
|
|
}
|
|
|
|
if (ah->caldata)
|
|
ah->caldata->CalValid = 0;
|
|
|
|
return true;
|
|
}
|
|
|
|
static const struct ath9k_percal_data iq_cal_multi_sample = {
|
|
IQ_MISMATCH_CAL,
|
|
MAX_CAL_SAMPLES,
|
|
PER_MIN_LOG_COUNT,
|
|
ar9002_hw_iqcal_collect,
|
|
ar9002_hw_iqcalibrate
|
|
};
|
|
static const struct ath9k_percal_data iq_cal_single_sample = {
|
|
IQ_MISMATCH_CAL,
|
|
MIN_CAL_SAMPLES,
|
|
PER_MAX_LOG_COUNT,
|
|
ar9002_hw_iqcal_collect,
|
|
ar9002_hw_iqcalibrate
|
|
};
|
|
static const struct ath9k_percal_data adc_gain_cal_multi_sample = {
|
|
ADC_GAIN_CAL,
|
|
MAX_CAL_SAMPLES,
|
|
PER_MIN_LOG_COUNT,
|
|
ar9002_hw_adc_gaincal_collect,
|
|
ar9002_hw_adc_gaincal_calibrate
|
|
};
|
|
static const struct ath9k_percal_data adc_gain_cal_single_sample = {
|
|
ADC_GAIN_CAL,
|
|
MIN_CAL_SAMPLES,
|
|
PER_MAX_LOG_COUNT,
|
|
ar9002_hw_adc_gaincal_collect,
|
|
ar9002_hw_adc_gaincal_calibrate
|
|
};
|
|
static const struct ath9k_percal_data adc_dc_cal_multi_sample = {
|
|
ADC_DC_CAL,
|
|
MAX_CAL_SAMPLES,
|
|
PER_MIN_LOG_COUNT,
|
|
ar9002_hw_adc_dccal_collect,
|
|
ar9002_hw_adc_dccal_calibrate
|
|
};
|
|
static const struct ath9k_percal_data adc_dc_cal_single_sample = {
|
|
ADC_DC_CAL,
|
|
MIN_CAL_SAMPLES,
|
|
PER_MAX_LOG_COUNT,
|
|
ar9002_hw_adc_dccal_collect,
|
|
ar9002_hw_adc_dccal_calibrate
|
|
};
|
|
|
|
static void ar9002_hw_init_cal_settings(struct ath_hw *ah)
|
|
{
|
|
if (AR_SREV_9100(ah)) {
|
|
ah->iq_caldata.calData = &iq_cal_multi_sample;
|
|
ah->supp_cals = IQ_MISMATCH_CAL;
|
|
return;
|
|
}
|
|
|
|
if (AR_SREV_9160_10_OR_LATER(ah)) {
|
|
if (AR_SREV_9280_20_OR_LATER(ah)) {
|
|
ah->iq_caldata.calData = &iq_cal_single_sample;
|
|
ah->adcgain_caldata.calData =
|
|
&adc_gain_cal_single_sample;
|
|
ah->adcdc_caldata.calData =
|
|
&adc_dc_cal_single_sample;
|
|
} else {
|
|
ah->iq_caldata.calData = &iq_cal_multi_sample;
|
|
ah->adcgain_caldata.calData =
|
|
&adc_gain_cal_multi_sample;
|
|
ah->adcdc_caldata.calData =
|
|
&adc_dc_cal_multi_sample;
|
|
}
|
|
ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
|
|
}
|
|
}
|
|
|
|
void ar9002_hw_attach_calib_ops(struct ath_hw *ah)
|
|
{
|
|
struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
|
|
struct ath_hw_ops *ops = ath9k_hw_ops(ah);
|
|
|
|
priv_ops->init_cal_settings = ar9002_hw_init_cal_settings;
|
|
priv_ops->init_cal = ar9002_hw_init_cal;
|
|
priv_ops->setup_calibration = ar9002_hw_setup_calibration;
|
|
priv_ops->iscal_supported = ar9002_hw_iscal_supported;
|
|
|
|
ops->calibrate = ar9002_hw_calibrate;
|
|
}
|