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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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8faf2e6c20
Several MIPS platforms don't set pci_controller::io_map_base for their PCI bridges. This results in a panic in pci_iomap(). (The panic is conditional on CONFIG_PCI_DOMAINS, but that is now enabled for all PCI MIPS systems.) Signed-off-by: Ben Hutchings <ben@decadent.org.uk> Cc: linux-mips@linux-mips.org Cc: Martin Michlmayr <tbm@cyrius.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: 584784@bugs.debian.org Patchwork: https://patchwork.linux-mips.org/patch/1377/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
68 lines
1.7 KiB
C
68 lines
1.7 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <asm/titan_dep.h>
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extern struct pci_ops titan_pci_ops;
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static struct resource py_mem_resource = {
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.start = 0xe0000000UL,
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.end = 0xe3ffffffUL,
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.name = "Titan PCI MEM",
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.flags = IORESOURCE_MEM
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};
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/*
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* PMON really reserves 16MB of I/O port space but that's stupid, nothing
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* needs that much since allocations are limited to 256 bytes per device
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* anyway. So we just claim 64kB here.
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*/
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#define TITAN_IO_SIZE 0x0000ffffUL
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#define TITAN_IO_BASE 0xe8000000UL
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static struct resource py_io_resource = {
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.start = 0x00001000UL,
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.end = TITAN_IO_SIZE - 1,
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.name = "Titan IO MEM",
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.flags = IORESOURCE_IO,
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};
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static struct pci_controller py_controller = {
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.pci_ops = &titan_pci_ops,
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.mem_resource = &py_mem_resource,
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.mem_offset = 0x00000000UL,
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.io_resource = &py_io_resource,
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.io_offset = 0x00000000UL
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};
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static char ioremap_failed[] __initdata = "Could not ioremap I/O port range";
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static int __init pmc_yosemite_setup(void)
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{
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unsigned long io_v_base;
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io_v_base = (unsigned long) ioremap(TITAN_IO_BASE, TITAN_IO_SIZE);
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if (!io_v_base)
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panic(ioremap_failed);
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set_io_port_base(io_v_base);
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py_controller.io_map_base = io_v_base;
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TITAN_WRITE(RM9000x2_OCD_LKM7, TITAN_READ(RM9000x2_OCD_LKM7) | 1);
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ioport_resource.end = TITAN_IO_SIZE - 1;
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register_pci_controller(&py_controller);
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return 0;
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}
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arch_initcall(pmc_yosemite_setup);
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