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		52650505fb
		
	
	
	
	
		
			
			The OMAP1 clock code currently #includes a large .h file full of static
data structures.  Instead, define the data in a .c file.
Russell King <linux@arm.linux.org.uk> proposed this new arrangement:
    http://marc.info/?l=linux-omap&m=125967425908895&w=2
This patch also deals with most of the flagrant checkpatch violations.
While here, separate the mpu_rate data structures out into their own
files, opp.h and opp_data.c.  In the long run, these mpu_rate tables
should be replaced with OPP code.
Also includes a patch from Felipe Balbi <felipe.balbi@nokia.com> to
mark omap1_clk_functions as __initdata to avoid a section warning:
    http://patchwork.kernel.org/patch/64366/
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Felipe Balbi <felipe.balbi@nokia.com>
Cc: Nishanth Menon <nm@ti.com>
		
	
			
		
			
				
	
	
		
			60 lines
		
	
	
		
			2.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			60 lines
		
	
	
		
			2.2 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  *  linux/arch/arm/mach-omap1/opp_data.c
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|  *
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|  *  Copyright (C) 2004 - 2005 Nokia corporation
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|  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
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|  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
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|  *
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|  * This program is free software; you can redistribute it and/or modify
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|  * it under the terms of the GNU General Public License version 2 as
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|  * published by the Free Software Foundation.
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|  */
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| 
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| #include "opp.h"
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| 
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| /*-------------------------------------------------------------------------
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|  * Omap1 MPU rate table
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|  *-------------------------------------------------------------------------*/
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| struct mpu_rate omap1_rate_table[] = {
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| 	/* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
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| 	 * NOTE: Comment order here is different from bits in CKCTL value:
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| 	 * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
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| 	 */
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| #if defined(CONFIG_OMAP_ARM_216MHZ)
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| 	{ 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
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| #endif
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| #if defined(CONFIG_OMAP_ARM_195MHZ)
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| 	{ 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
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| #endif
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| #if defined(CONFIG_OMAP_ARM_192MHZ)
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| 	{ 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
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| 	{ 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
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| 	{  96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
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| 	{  48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */
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| 	{  24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
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| #endif
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| #if defined(CONFIG_OMAP_ARM_182MHZ)
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| 	{ 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
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| #endif
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| #if defined(CONFIG_OMAP_ARM_168MHZ)
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| 	{ 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
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| #endif
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| #if defined(CONFIG_OMAP_ARM_150MHZ)
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| 	{ 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
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| #endif
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| #if defined(CONFIG_OMAP_ARM_120MHZ)
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| 	{ 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
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| #endif
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| #if defined(CONFIG_OMAP_ARM_96MHZ)
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| 	{  96000000, 12000000,  96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
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| #endif
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| #if defined(CONFIG_OMAP_ARM_60MHZ)
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| 	{  60000000, 12000000,  60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
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| #endif
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| #if defined(CONFIG_OMAP_ARM_30MHZ)
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| 	{  30000000, 12000000,  60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
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| #endif
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| 	{ 0, 0, 0, 0, 0 },
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| };
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| 
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