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a439fe51a1
The majority of this patch was created by the following script: *** ASM=arch/sparc/include/asm mkdir -p $ASM git mv include/asm-sparc64/ftrace.h $ASM git rm include/asm-sparc64/* git mv include/asm-sparc/* $ASM sed -ie 's/asm-sparc64/asm/g' $ASM/* sed -ie 's/asm-sparc/asm/g' $ASM/* *** The rest was an update of the top-level Makefile to use sparc for header files when sparc64 is being build. And a small fixlet to pick up the correct unistd.h from sparc64 code. Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
254 lines
8.1 KiB
C
254 lines
8.1 KiB
C
/*
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* viking.h: Defines specific to the GNU/Viking MBUS module.
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* This is SRMMU stuff.
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*
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* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
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*/
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#ifndef _SPARC_VIKING_H
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#define _SPARC_VIKING_H
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#include <asm/asi.h>
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#include <asm/mxcc.h>
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#include <asm/pgtsrmmu.h>
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/* Bits in the SRMMU control register for GNU/Viking modules.
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*
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* -----------------------------------------------------------
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* |impl-vers| RSV |TC|AC|SP|BM|PC|MBM|SB|IC|DC|PSO|RSV|NF|ME|
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* -----------------------------------------------------------
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* 31 24 23-17 16 15 14 13 12 11 10 9 8 7 6-2 1 0
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*
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* TC: Tablewalk Cacheable -- 0 = Twalks are not cacheable in E-cache
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* 1 = Twalks are cacheable in E-cache
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*
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* GNU/Viking will only cache tablewalks in the E-cache (mxcc) if present
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* and never caches them internally (or so states the docs). Therefore
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* for machines lacking an E-cache (ie. in MBUS mode) this bit must
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* remain cleared.
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*
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* AC: Alternate Cacheable -- 0 = Passthru physical accesses not cacheable
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* 1 = Passthru physical accesses cacheable
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*
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* This indicates whether accesses are cacheable when no cachable bit
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* is present in the pte when the processor is in boot-mode or the
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* access does not need pte's for translation (ie. pass-thru ASI's).
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* "Cachable" is only referring to E-cache (if present) and not the
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* on chip split I/D caches of the GNU/Viking.
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*
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* SP: SnooP Enable -- 0 = bus snooping off, 1 = bus snooping on
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*
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* This enables snooping on the GNU/Viking bus. This must be on
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* for the hardware cache consistency mechanisms of the GNU/Viking
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* to work at all. On non-mxcc GNU/Viking modules the split I/D
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* caches will snoop regardless of whether they are enabled, this
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* takes care of the case where the I or D or both caches are turned
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* off yet still contain valid data. Note also that this bit does
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* not affect GNU/Viking store-buffer snoops, those happen if the
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* store-buffer is enabled no matter what.
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*
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* BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode
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*
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* This indicates whether the GNU/Viking is in boot-mode or not,
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* if it is then all instruction fetch physical addresses are
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* computed as 0xff0000000 + low 28 bits of requested address.
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* GNU/Viking boot-mode does not affect data accesses. Also,
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* in boot mode instruction accesses bypass the split on chip I/D
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* caches, they may be cached by the GNU/MXCC if present and enabled.
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*
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* MBM: MBus Mode -- 0 = not in MBus mode, 1 = in MBus mode
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*
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* This indicated the GNU/Viking configuration present. If in
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* MBUS mode, the GNU/Viking lacks a GNU/MXCC E-cache. If it is
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* not then the GNU/Viking is on a module VBUS connected directly
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* to a GNU/MXCC cache controller. The GNU/MXCC can be thus connected
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* to either an GNU/MBUS (sun4m) or the packet-switched GNU/XBus (sun4d).
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*
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* SB: StoreBuffer enable -- 0 = store buffer off, 1 = store buffer on
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*
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* The GNU/Viking store buffer allows the chip to continue execution
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* after a store even if the data cannot be placed in one of the
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* caches during that cycle. If disabled, all stores operations
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* occur synchronously.
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*
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* IC: Instruction Cache -- 0 = off, 1 = on
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* DC: Data Cache -- 0 = off, 1 = 0n
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*
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* These bits enable the on-cpu GNU/Viking split I/D caches. Note,
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* as mentioned above, these caches will snoop the bus in GNU/MBUS
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* configurations even when disabled to avoid data corruption.
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*
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* NF: No Fault -- 0 = faults generate traps, 1 = faults don't trap
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* ME: MMU enable -- 0 = mmu not translating, 1 = mmu translating
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*
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*/
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#define VIKING_MMUENABLE 0x00000001
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#define VIKING_NOFAULT 0x00000002
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#define VIKING_PSO 0x00000080
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#define VIKING_DCENABLE 0x00000100 /* Enable data cache */
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#define VIKING_ICENABLE 0x00000200 /* Enable instruction cache */
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#define VIKING_SBENABLE 0x00000400 /* Enable store buffer */
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#define VIKING_MMODE 0x00000800 /* MBUS mode */
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#define VIKING_PCENABLE 0x00001000 /* Enable parity checking */
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#define VIKING_BMODE 0x00002000
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#define VIKING_SPENABLE 0x00004000 /* Enable bus cache snooping */
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#define VIKING_ACENABLE 0x00008000 /* Enable alternate caching */
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#define VIKING_TCENABLE 0x00010000 /* Enable table-walks to be cached */
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#define VIKING_DPENABLE 0x00040000 /* Enable the data prefetcher */
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/*
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* GNU/Viking Breakpoint Action Register fields.
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*/
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#define VIKING_ACTION_MIX 0x00001000 /* Enable multiple instructions */
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/*
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* GNU/Viking Cache Tags.
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*/
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#define VIKING_PTAG_VALID 0x01000000 /* Cache block is valid */
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#define VIKING_PTAG_DIRTY 0x00010000 /* Block has been modified */
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#define VIKING_PTAG_SHARED 0x00000100 /* Shared with some other cache */
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#ifndef __ASSEMBLY__
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static inline void viking_flush_icache(void)
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{
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__asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
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: /* no outputs */
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: "i" (ASI_M_IC_FLCLEAR)
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: "memory");
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}
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static inline void viking_flush_dcache(void)
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{
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__asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
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: /* no outputs */
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: "i" (ASI_M_DC_FLCLEAR)
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: "memory");
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}
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static inline void viking_unlock_icache(void)
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{
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__asm__ __volatile__("sta %%g0, [%0] %1\n\t"
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: /* no outputs */
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: "r" (0x80000000), "i" (ASI_M_IC_FLCLEAR)
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: "memory");
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}
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static inline void viking_unlock_dcache(void)
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{
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__asm__ __volatile__("sta %%g0, [%0] %1\n\t"
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: /* no outputs */
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: "r" (0x80000000), "i" (ASI_M_DC_FLCLEAR)
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: "memory");
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}
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static inline void viking_set_bpreg(unsigned long regval)
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{
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__asm__ __volatile__("sta %0, [%%g0] %1\n\t"
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: /* no outputs */
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: "r" (regval), "i" (ASI_M_ACTION)
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: "memory");
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}
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static inline unsigned long viking_get_bpreg(void)
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{
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unsigned long regval;
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__asm__ __volatile__("lda [%%g0] %1, %0\n\t"
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: "=r" (regval)
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: "i" (ASI_M_ACTION));
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return regval;
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}
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static inline void viking_get_dcache_ptag(int set, int block,
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unsigned long *data)
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{
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unsigned long ptag = ((set & 0x7f) << 5) | ((block & 0x3) << 26) |
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0x80000000;
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unsigned long info, page;
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__asm__ __volatile__ ("ldda [%2] %3, %%g2\n\t"
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"or %%g0, %%g2, %0\n\t"
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"or %%g0, %%g3, %1\n\t"
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: "=r" (info), "=r" (page)
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: "r" (ptag), "i" (ASI_M_DATAC_TAG)
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: "g2", "g3");
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data[0] = info;
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data[1] = page;
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}
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static inline void viking_mxcc_turn_off_parity(unsigned long *mregp,
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unsigned long *mxcc_cregp)
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{
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unsigned long mreg = *mregp;
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unsigned long mxcc_creg = *mxcc_cregp;
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mreg &= ~(VIKING_PCENABLE);
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mxcc_creg &= ~(MXCC_CTL_PARE);
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__asm__ __volatile__ ("set 1f, %%g2\n\t"
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"andcc %%g2, 4, %%g0\n\t"
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"bne 2f\n\t"
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" nop\n"
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"1:\n\t"
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"sta %0, [%%g0] %3\n\t"
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"sta %1, [%2] %4\n\t"
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"b 1f\n\t"
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" nop\n\t"
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"nop\n"
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"2:\n\t"
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"sta %0, [%%g0] %3\n\t"
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"sta %1, [%2] %4\n"
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"1:\n\t"
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: /* no output */
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: "r" (mreg), "r" (mxcc_creg),
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"r" (MXCC_CREG), "i" (ASI_M_MMUREGS),
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"i" (ASI_M_MXCC)
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: "g2", "memory", "cc");
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*mregp = mreg;
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*mxcc_cregp = mxcc_creg;
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}
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static inline unsigned long viking_hwprobe(unsigned long vaddr)
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{
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unsigned long val;
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vaddr &= PAGE_MASK;
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/* Probe all MMU entries. */
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__asm__ __volatile__("lda [%1] %2, %0\n\t"
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: "=r" (val)
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: "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
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if (!val)
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return 0;
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/* Probe region. */
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__asm__ __volatile__("lda [%1] %2, %0\n\t"
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: "=r" (val)
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: "r" (vaddr | 0x200), "i" (ASI_M_FLUSH_PROBE));
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if ((val & SRMMU_ET_MASK) == SRMMU_ET_PTE) {
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vaddr &= ~SRMMU_PGDIR_MASK;
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vaddr >>= PAGE_SHIFT;
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return val | (vaddr << 8);
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}
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/* Probe segment. */
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__asm__ __volatile__("lda [%1] %2, %0\n\t"
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: "=r" (val)
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: "r" (vaddr | 0x100), "i" (ASI_M_FLUSH_PROBE));
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if ((val & SRMMU_ET_MASK) == SRMMU_ET_PTE) {
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vaddr &= ~SRMMU_REAL_PMD_MASK;
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vaddr >>= PAGE_SHIFT;
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return val | (vaddr << 8);
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}
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/* Probe page. */
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__asm__ __volatile__("lda [%1] %2, %0\n\t"
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: "=r" (val)
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: "r" (vaddr), "i" (ASI_M_FLUSH_PROBE));
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return val;
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}
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#endif /* !__ASSEMBLY__ */
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#endif /* !(_SPARC_VIKING_H) */
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