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	 2856f5e31c
			
		
	
	
		2856f5e31c
		
	
	
	
	
		
			
			atomic_add_unless as inline. Remove system.h atomic.h circular dependency. I agree (with Andi Kleen) this typeof is not needed and more error prone. All the original atomic.h code that uses cmpxchg (which includes the atomic_add_unless) uses defines instead of inline functions, probably to circumvent a circular dependency between system.h and atomic.h on powerpc (which my patch addresses). Therefore, it makes sense to use inline functions that will provide type checking. atomic_add_unless as inline. Remove system.h atomic.h circular dependency. Digging into the FRV architecture shows me that it is also affected by such a circular dependency. Here is the diff applying this against the rest of my atomic.h patches. It applies over the atomic.h standardization patches. Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
		
			
				
	
	
		
			198 lines
		
	
	
		
			4.0 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			198 lines
		
	
	
		
			4.0 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| #ifndef __ARCH_M68K_ATOMIC__
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| #define __ARCH_M68K_ATOMIC__
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| 
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| 
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| #include <asm/system.h>
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| 
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| /*
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|  * Atomic operations that C can't guarantee us.  Useful for
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|  * resource counting etc..
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|  */
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| 
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| /*
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|  * We do not have SMP m68k systems, so we don't have to deal with that.
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|  */
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| 
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| typedef struct { int counter; } atomic_t;
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| #define ATOMIC_INIT(i)	{ (i) }
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| 
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| #define atomic_read(v)		((v)->counter)
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| #define atomic_set(v, i)	(((v)->counter) = i)
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| 
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| static inline void atomic_add(int i, atomic_t *v)
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| {
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| 	__asm__ __volatile__("addl %1,%0" : "+m" (*v) : "id" (i));
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| }
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| 
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| static inline void atomic_sub(int i, atomic_t *v)
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| {
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| 	__asm__ __volatile__("subl %1,%0" : "+m" (*v) : "id" (i));
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| }
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| 
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| static inline void atomic_inc(atomic_t *v)
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| {
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| 	__asm__ __volatile__("addql #1,%0" : "+m" (*v));
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| }
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| 
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| static inline void atomic_dec(atomic_t *v)
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| {
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| 	__asm__ __volatile__("subql #1,%0" : "+m" (*v));
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| }
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| 
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| static inline int atomic_dec_and_test(atomic_t *v)
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| {
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| 	char c;
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| 	__asm__ __volatile__("subql #1,%1; seq %0" : "=d" (c), "+m" (*v));
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| 	return c != 0;
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| }
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| 
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| static inline int atomic_inc_and_test(atomic_t *v)
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| {
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| 	char c;
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| 	__asm__ __volatile__("addql #1,%1; seq %0" : "=d" (c), "+m" (*v));
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| 	return c != 0;
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| }
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| 
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| #ifdef CONFIG_RMW_INSNS
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| 
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| static inline int atomic_add_return(int i, atomic_t *v)
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| {
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| 	int t, tmp;
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| 
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| 	__asm__ __volatile__(
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| 			"1:	movel %2,%1\n"
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| 			"	addl %3,%1\n"
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| 			"	casl %2,%1,%0\n"
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| 			"	jne 1b"
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| 			: "+m" (*v), "=&d" (t), "=&d" (tmp)
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| 			: "g" (i), "2" (atomic_read(v)));
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| 	return t;
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| }
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| 
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| static inline int atomic_sub_return(int i, atomic_t *v)
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| {
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| 	int t, tmp;
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| 
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| 	__asm__ __volatile__(
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| 			"1:	movel %2,%1\n"
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| 			"	subl %3,%1\n"
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| 			"	casl %2,%1,%0\n"
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| 			"	jne 1b"
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| 			: "+m" (*v), "=&d" (t), "=&d" (tmp)
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| 			: "g" (i), "2" (atomic_read(v)));
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| 	return t;
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| }
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| 
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| #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
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| #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
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| 
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| #else /* !CONFIG_RMW_INSNS */
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| 
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| static inline int atomic_add_return(int i, atomic_t * v)
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| {
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| 	unsigned long flags;
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| 	int t;
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| 
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| 	local_irq_save(flags);
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| 	t = atomic_read(v);
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| 	t += i;
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| 	atomic_set(v, t);
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| 	local_irq_restore(flags);
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| 
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| 	return t;
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| }
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| 
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| static inline int atomic_sub_return(int i, atomic_t * v)
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| {
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| 	unsigned long flags;
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| 	int t;
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| 
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| 	local_irq_save(flags);
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| 	t = atomic_read(v);
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| 	t -= i;
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| 	atomic_set(v, t);
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| 	local_irq_restore(flags);
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| 
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| 	return t;
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| }
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| 
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| static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
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| {
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| 	unsigned long flags;
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| 	int prev;
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| 
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| 	local_irq_save(flags);
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| 	prev = atomic_read(v);
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| 	if (prev == old)
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| 		atomic_set(v, new);
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| 	local_irq_restore(flags);
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| 	return prev;
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| }
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| 
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| static inline int atomic_xchg(atomic_t *v, int new)
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| {
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| 	unsigned long flags;
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| 	int prev;
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| 
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| 	local_irq_save(flags);
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| 	prev = atomic_read(v);
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| 	atomic_set(v, new);
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| 	local_irq_restore(flags);
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| 	return prev;
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| }
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| 
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| #endif /* !CONFIG_RMW_INSNS */
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| 
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| #define atomic_dec_return(v)	atomic_sub_return(1, (v))
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| #define atomic_inc_return(v)	atomic_add_return(1, (v))
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| 
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| static inline int atomic_sub_and_test(int i, atomic_t *v)
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| {
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| 	char c;
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| 	__asm__ __volatile__("subl %2,%1; seq %0" : "=d" (c), "+m" (*v): "g" (i));
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| 	return c != 0;
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| }
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| 
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| static inline int atomic_add_negative(int i, atomic_t *v)
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| {
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| 	char c;
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| 	__asm__ __volatile__("addl %2,%1; smi %0" : "=d" (c), "+m" (*v): "g" (i));
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| 	return c != 0;
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| }
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| 
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| static inline void atomic_clear_mask(unsigned long mask, unsigned long *v)
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| {
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| 	__asm__ __volatile__("andl %1,%0" : "+m" (*v) : "id" (~(mask)));
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| }
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| 
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| static inline void atomic_set_mask(unsigned long mask, unsigned long *v)
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| {
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| 	__asm__ __volatile__("orl %1,%0" : "+m" (*v) : "id" (mask));
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| }
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| 
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| static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
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| {
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| 	int c, old;
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| 	c = atomic_read(v);
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| 	for (;;) {
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| 		if (unlikely(c == (u)))
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| 			break;
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| 		old = atomic_cmpxchg((v), c, c + (a));
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| 		if (likely(old == c))
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| 			break;
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| 		c = old;
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| 	}
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| 	return c != (u);
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| }
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| 
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| #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
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| 
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| /* Atomic operations are already serializing */
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| #define smp_mb__before_atomic_dec()	barrier()
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| #define smp_mb__after_atomic_dec()	barrier()
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| #define smp_mb__before_atomic_inc()	barrier()
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| #define smp_mb__after_atomic_inc()	barrier()
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| 
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| #include <asm-generic/atomic.h>
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| #endif /* __ARCH_M68K_ATOMIC __ */
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