mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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2f82af08fc
Due to problems at cam.org, my nico@cam.org email address is no longer valid. FRom now on, nico@fluxnic.net should be used instead. Signed-off-by: Nicolas Pitre <nico@fluxnic.net> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
48 lines
1.2 KiB
ArmAsm
48 lines
1.2 KiB
ArmAsm
/*
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* linux/arch/arm/boot/compressed/head-sa1100.S
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*
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* Copyright (C) 1999 Nicolas Pitre <nico@fluxnic.net>
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*
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* SA1100 specific tweaks. This is merged into head.S by the linker.
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*
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*/
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#include <linux/linkage.h>
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#include <asm/mach-types.h>
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.section ".start", "ax"
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__SA1100_start:
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@ Preserve r8/r7 i.e. kernel entry values
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#ifdef CONFIG_SA1100_COLLIE
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mov r7, #MACH_TYPE_COLLIE
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#endif
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#ifdef CONFIG_SA1100_SIMPAD
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@ UNTIL we've something like an open bootldr
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mov r7, #MACH_TYPE_SIMPAD @should be 87
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#endif
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mrc p15, 0, r0, c1, c0, 0 @ read control reg
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ands r0, r0, #0x0d
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beq 99f
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@ Data cache might be active.
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@ Be sure to flush kernel binary out of the cache,
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@ whatever state it is, before it is turned off.
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@ This is done by fetching through currently executed
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@ memory to be sure we hit the same cache.
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bic r2, pc, #0x1f
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add r3, r2, #0x4000 @ 16 kb is quite enough...
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1: ldr r0, [r2], #32
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teq r2, r3
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bne 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
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@ disabling MMU and caches
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mrc p15, 0, r0, c1, c0, 0 @ read control reg
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bic r0, r0, #0x0d @ clear WB, DC, MMU
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bic r0, r0, #0x1000 @ clear Icache
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mcr p15, 0, r0, c1, c0, 0
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99:
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