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	 2c08583c6a
			
		
	
	
		2c08583c6a
		
	
	
	
	
		
			
			This patch fixes a build failure[1], by adding the missing semaphore.h include References: [1] http://kisskb.ellerman.id.au/kisskb/buildresult/2234322/ Signed-off-by: Peter Huewe <peterhuewe@gmx.de> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
		
			
				
	
	
		
			260 lines
		
	
	
		
			6.8 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			260 lines
		
	
	
		
			6.8 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  *  linux/include/mfd/ucb1x00.h
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|  *
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|  *  Copyright (C) 2001 Russell King, All Rights Reserved.
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|  *
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|  * This program is free software; you can redistribute it and/or modify
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|  * it under the terms of the GNU General Public License as published by
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|  * the Free Software Foundation; either version 2 of the License.
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|  */
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| #ifndef UCB1200_H
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| #define UCB1200_H
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| 
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| #include <linux/mfd/mcp.h>
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| #include <linux/gpio.h>
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| #include <linux/semaphore.h>
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| 
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| #define UCB_IO_DATA	0x00
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| #define UCB_IO_DIR	0x01
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| 
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| #define UCB_IO_0		(1 << 0)
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| #define UCB_IO_1		(1 << 1)
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| #define UCB_IO_2		(1 << 2)
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| #define UCB_IO_3		(1 << 3)
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| #define UCB_IO_4		(1 << 4)
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| #define UCB_IO_5		(1 << 5)
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| #define UCB_IO_6		(1 << 6)
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| #define UCB_IO_7		(1 << 7)
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| #define UCB_IO_8		(1 << 8)
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| #define UCB_IO_9		(1 << 9)
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| 
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| #define UCB_IE_RIS	0x02
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| #define UCB_IE_FAL	0x03
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| #define UCB_IE_STATUS	0x04
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| #define UCB_IE_CLEAR	0x04
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| #define UCB_IE_ADC		(1 << 11)
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| #define UCB_IE_TSPX		(1 << 12)
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| #define UCB_IE_TSMX		(1 << 13)
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| #define UCB_IE_TCLIP		(1 << 14)
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| #define UCB_IE_ACLIP		(1 << 15)
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| 
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| #define UCB_IRQ_TSPX		12
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| 
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| #define UCB_TC_A	0x05
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| #define UCB_TC_A_LOOP		(1 << 7)	/* UCB1200 */
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| #define UCB_TC_A_AMPL		(1 << 7)	/* UCB1300 */
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| 
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| #define UCB_TC_B	0x06
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| #define UCB_TC_B_VOICE_ENA	(1 << 3)
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| #define UCB_TC_B_CLIP		(1 << 4)
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| #define UCB_TC_B_ATT		(1 << 6)
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| #define UCB_TC_B_SIDE_ENA	(1 << 11)
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| #define UCB_TC_B_MUTE		(1 << 13)
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| #define UCB_TC_B_IN_ENA		(1 << 14)
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| #define UCB_TC_B_OUT_ENA	(1 << 15)
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| 
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| #define UCB_AC_A	0x07
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| #define UCB_AC_B	0x08
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| #define UCB_AC_B_LOOP		(1 << 8)
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| #define UCB_AC_B_MUTE		(1 << 13)
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| #define UCB_AC_B_IN_ENA		(1 << 14)
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| #define UCB_AC_B_OUT_ENA	(1 << 15)
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| 
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| #define UCB_TS_CR	0x09
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| #define UCB_TS_CR_TSMX_POW	(1 << 0)
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| #define UCB_TS_CR_TSPX_POW	(1 << 1)
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| #define UCB_TS_CR_TSMY_POW	(1 << 2)
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| #define UCB_TS_CR_TSPY_POW	(1 << 3)
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| #define UCB_TS_CR_TSMX_GND	(1 << 4)
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| #define UCB_TS_CR_TSPX_GND	(1 << 5)
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| #define UCB_TS_CR_TSMY_GND	(1 << 6)
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| #define UCB_TS_CR_TSPY_GND	(1 << 7)
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| #define UCB_TS_CR_MODE_INT	(0 << 8)
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| #define UCB_TS_CR_MODE_PRES	(1 << 8)
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| #define UCB_TS_CR_MODE_POS	(2 << 8)
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| #define UCB_TS_CR_BIAS_ENA	(1 << 11)
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| #define UCB_TS_CR_TSPX_LOW	(1 << 12)
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| #define UCB_TS_CR_TSMX_LOW	(1 << 13)
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| 
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| #define UCB_ADC_CR	0x0a
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| #define UCB_ADC_SYNC_ENA	(1 << 0)
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| #define UCB_ADC_VREFBYP_CON	(1 << 1)
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| #define UCB_ADC_INP_TSPX	(0 << 2)
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| #define UCB_ADC_INP_TSMX	(1 << 2)
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| #define UCB_ADC_INP_TSPY	(2 << 2)
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| #define UCB_ADC_INP_TSMY	(3 << 2)
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| #define UCB_ADC_INP_AD0		(4 << 2)
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| #define UCB_ADC_INP_AD1		(5 << 2)
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| #define UCB_ADC_INP_AD2		(6 << 2)
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| #define UCB_ADC_INP_AD3		(7 << 2)
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| #define UCB_ADC_EXT_REF		(1 << 5)
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| #define UCB_ADC_START		(1 << 7)
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| #define UCB_ADC_ENA		(1 << 15)
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| 
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| #define UCB_ADC_DATA	0x0b
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| #define UCB_ADC_DAT_VAL		(1 << 15)
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| #define UCB_ADC_DAT(x)		(((x) & 0x7fe0) >> 5)
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| 
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| #define UCB_ID		0x0c
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| #define UCB_ID_1200		0x1004
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| #define UCB_ID_1300		0x1005
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| #define UCB_ID_TC35143          0x9712
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| 
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| #define UCB_MODE	0x0d
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| #define UCB_MODE_DYN_VFLAG_ENA	(1 << 12)
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| #define UCB_MODE_AUD_OFF_CAN	(1 << 13)
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| 
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| 
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| struct ucb1x00_irq {
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| 	void *devid;
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| 	void (*fn)(int, void *);
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| };
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| 
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| struct ucb1x00 {
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| 	spinlock_t		lock;
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| 	struct mcp		*mcp;
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| 	unsigned int		irq;
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| 	struct semaphore	adc_sem;
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| 	spinlock_t		io_lock;
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| 	u16			id;
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| 	u16			io_dir;
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| 	u16			io_out;
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| 	u16			adc_cr;
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| 	u16			irq_fal_enbl;
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| 	u16			irq_ris_enbl;
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| 	struct ucb1x00_irq	irq_handler[16];
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| 	struct device		dev;
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| 	struct list_head	node;
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| 	struct list_head	devs;
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| 	struct gpio_chip 	gpio;
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| };
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| 
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| struct ucb1x00_driver;
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| 
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| struct ucb1x00_dev {
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| 	struct list_head	dev_node;
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| 	struct list_head	drv_node;
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| 	struct ucb1x00		*ucb;
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| 	struct ucb1x00_driver	*drv;
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| 	void			*priv;
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| };
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| 
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| struct ucb1x00_driver {
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| 	struct list_head	node;
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| 	struct list_head	devs;
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| 	int	(*add)(struct ucb1x00_dev *dev);
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| 	void	(*remove)(struct ucb1x00_dev *dev);
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| 	int	(*suspend)(struct ucb1x00_dev *dev, pm_message_t state);
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| 	int	(*resume)(struct ucb1x00_dev *dev);
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| };
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| 
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| #define classdev_to_ucb1x00(cd)	container_of(cd, struct ucb1x00, dev)
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| 
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| int ucb1x00_register_driver(struct ucb1x00_driver *);
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| void ucb1x00_unregister_driver(struct ucb1x00_driver *);
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| 
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| /**
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|  *	ucb1x00_clkrate - return the UCB1x00 SIB clock rate
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|  *	@ucb: UCB1x00 structure describing chip
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|  *
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|  *	Return the SIB clock rate in Hz.
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|  */
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| static inline unsigned int ucb1x00_clkrate(struct ucb1x00 *ucb)
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| {
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| 	return mcp_get_sclk_rate(ucb->mcp);
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| }
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| 
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| /**
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|  *	ucb1x00_enable - enable the UCB1x00 SIB clock
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|  *	@ucb: UCB1x00 structure describing chip
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|  *
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|  *	Enable the SIB clock.  This can be called multiple times.
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|  */
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| static inline void ucb1x00_enable(struct ucb1x00 *ucb)
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| {
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| 	mcp_enable(ucb->mcp);
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| }
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| 
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| /**
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|  *	ucb1x00_disable - disable the UCB1x00 SIB clock
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|  *	@ucb: UCB1x00 structure describing chip
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|  *
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|  *	Disable the SIB clock.  The SIB clock will only be disabled
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|  *	when the number of ucb1x00_enable calls match the number of
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|  *	ucb1x00_disable calls.
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|  */
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| static inline void ucb1x00_disable(struct ucb1x00 *ucb)
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| {
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| 	mcp_disable(ucb->mcp);
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| }
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| 
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| /**
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|  *	ucb1x00_reg_write - write a UCB1x00 register
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|  *	@ucb: UCB1x00 structure describing chip
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|  *	@reg: UCB1x00 4-bit register index to write
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|  *	@val: UCB1x00 16-bit value to write
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|  *
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|  *	Write the UCB1x00 register @reg with value @val.  The SIB
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|  *	clock must be running for this function to return.
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|  */
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| static inline void ucb1x00_reg_write(struct ucb1x00 *ucb, unsigned int reg, unsigned int val)
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| {
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| 	mcp_reg_write(ucb->mcp, reg, val);
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| }
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| 
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| /**
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|  *	ucb1x00_reg_read - read a UCB1x00 register
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|  *	@ucb: UCB1x00 structure describing chip
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|  *	@reg: UCB1x00 4-bit register index to write
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|  *
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|  *	Read the UCB1x00 register @reg and return its value.  The SIB
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|  *	clock must be running for this function to return.
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|  */
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| static inline unsigned int ucb1x00_reg_read(struct ucb1x00 *ucb, unsigned int reg)
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| {
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| 	return mcp_reg_read(ucb->mcp, reg);
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| }
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| /**
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|  *	ucb1x00_set_audio_divisor - 
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|  *	@ucb: UCB1x00 structure describing chip
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|  *	@div: SIB clock divisor
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|  */
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| static inline void ucb1x00_set_audio_divisor(struct ucb1x00 *ucb, unsigned int div)
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| {
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| 	mcp_set_audio_divisor(ucb->mcp, div);
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| }
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| 
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| /**
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|  *	ucb1x00_set_telecom_divisor -
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|  *	@ucb: UCB1x00 structure describing chip
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|  *	@div: SIB clock divisor
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|  */
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| static inline void ucb1x00_set_telecom_divisor(struct ucb1x00 *ucb, unsigned int div)
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| {
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| 	mcp_set_telecom_divisor(ucb->mcp, div);
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| }
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| 
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| void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int, unsigned int);
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| void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int, unsigned int);
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| unsigned int ucb1x00_io_read(struct ucb1x00 *ucb);
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| 
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| #define UCB_NOSYNC	(0)
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| #define UCB_SYNC	(1)
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| 
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| unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync);
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| void ucb1x00_adc_enable(struct ucb1x00 *ucb);
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| void ucb1x00_adc_disable(struct ucb1x00 *ucb);
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| 
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| /*
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|  * Which edges of the IRQ do you want to control today?
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|  */
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| #define UCB_RISING	(1 << 0)
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| #define UCB_FALLING	(1 << 1)
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| 
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| int ucb1x00_hook_irq(struct ucb1x00 *ucb, unsigned int idx, void (*fn)(int, void *), void *devid);
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| void ucb1x00_enable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges);
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| void ucb1x00_disable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges);
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| int ucb1x00_free_irq(struct ucb1x00 *ucb, unsigned int idx, void *devid);
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| 
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| #endif
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