mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-10-31 12:09:34 +00:00
df2a52a6c8
Clear PSS memory reset that is set as part of power-on-reset (pci reset). Complete PMM memory reset before BISTR start. Clear EDRAM BISTR start bit after fixed delay. BISTR DONE bit status is not getting set. Use a fixed 1ms delay for BISTR now. Expose PMM IT memory definitions to host. Signed-off-by: Jing Huang <huangj@brocade.com> Signed-off-by: James Bottomley <James.Bottomley@suse.de>
437 lines
12 KiB
C
437 lines
12 KiB
C
/*
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* Copyright (c) 2005-2009 Brocade Communications Systems, Inc.
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* All rights reserved
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* www.brocade.com
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*
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* Linux driver for Brocade Fibre Channel Host Bus Adapter.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License (GPL) Version 2 as
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* published by the Free Software Foundation
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#include <bfa.h>
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#include <bfa_ioc.h>
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#include <bfa_fwimg_priv.h>
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#include <cna/bfa_cna_trcmod.h>
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#include <cs/bfa_debug.h>
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#include <bfi/bfi_ioc.h>
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#include <bfi/bfi_ctreg.h>
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#include <log/bfa_log_hal.h>
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#include <defs/bfa_defs_pci.h>
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BFA_TRC_FILE(CNA, IOC_CT);
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/*
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* forward declarations
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*/
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static bfa_status_t bfa_ioc_ct_pll_init(struct bfa_ioc_s *ioc);
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static bfa_boolean_t bfa_ioc_ct_firmware_lock(struct bfa_ioc_s *ioc);
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static void bfa_ioc_ct_firmware_unlock(struct bfa_ioc_s *ioc);
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static void bfa_ioc_ct_reg_init(struct bfa_ioc_s *ioc);
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static void bfa_ioc_ct_map_port(struct bfa_ioc_s *ioc);
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static void bfa_ioc_ct_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix);
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static void bfa_ioc_ct_notify_hbfail(struct bfa_ioc_s *ioc);
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static void bfa_ioc_ct_ownership_reset(struct bfa_ioc_s *ioc);
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struct bfa_ioc_hwif_s hwif_ct;
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/**
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* Called from bfa_ioc_attach() to map asic specific calls.
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*/
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void
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bfa_ioc_set_ct_hwif(struct bfa_ioc_s *ioc)
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{
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hwif_ct.ioc_pll_init = bfa_ioc_ct_pll_init;
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hwif_ct.ioc_firmware_lock = bfa_ioc_ct_firmware_lock;
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hwif_ct.ioc_firmware_unlock = bfa_ioc_ct_firmware_unlock;
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hwif_ct.ioc_reg_init = bfa_ioc_ct_reg_init;
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hwif_ct.ioc_map_port = bfa_ioc_ct_map_port;
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hwif_ct.ioc_isr_mode_set = bfa_ioc_ct_isr_mode_set;
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hwif_ct.ioc_notify_hbfail = bfa_ioc_ct_notify_hbfail;
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hwif_ct.ioc_ownership_reset = bfa_ioc_ct_ownership_reset;
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ioc->ioc_hwif = &hwif_ct;
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}
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/**
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* Return true if firmware of current driver matches the running firmware.
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*/
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static bfa_boolean_t
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bfa_ioc_ct_firmware_lock(struct bfa_ioc_s *ioc)
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{
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enum bfi_ioc_state ioc_fwstate;
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u32 usecnt;
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struct bfi_ioc_image_hdr_s fwhdr;
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/**
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* Firmware match check is relevant only for CNA.
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*/
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if (!ioc->cna)
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return BFA_TRUE;
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/**
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* If bios boot (flash based) -- do not increment usage count
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*/
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if (bfi_image_get_size(BFA_IOC_FWIMG_TYPE(ioc)) < BFA_IOC_FWIMG_MINSZ)
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return BFA_TRUE;
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bfa_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg);
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usecnt = bfa_reg_read(ioc->ioc_regs.ioc_usage_reg);
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/**
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* If usage count is 0, always return TRUE.
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*/
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if (usecnt == 0) {
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bfa_reg_write(ioc->ioc_regs.ioc_usage_reg, 1);
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bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
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bfa_trc(ioc, usecnt);
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return BFA_TRUE;
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}
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ioc_fwstate = bfa_reg_read(ioc->ioc_regs.ioc_fwstate);
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bfa_trc(ioc, ioc_fwstate);
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/**
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* Use count cannot be non-zero and chip in uninitialized state.
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*/
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bfa_assert(ioc_fwstate != BFI_IOC_UNINIT);
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/**
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* Check if another driver with a different firmware is active
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*/
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bfa_ioc_fwver_get(ioc, &fwhdr);
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if (!bfa_ioc_fwver_cmp(ioc, &fwhdr)) {
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bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
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bfa_trc(ioc, usecnt);
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return BFA_FALSE;
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}
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/**
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* Same firmware version. Increment the reference count.
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*/
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usecnt++;
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bfa_reg_write(ioc->ioc_regs.ioc_usage_reg, usecnt);
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bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
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bfa_trc(ioc, usecnt);
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return BFA_TRUE;
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}
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static void
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bfa_ioc_ct_firmware_unlock(struct bfa_ioc_s *ioc)
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{
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u32 usecnt;
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/**
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* Firmware lock is relevant only for CNA.
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*/
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if (!ioc->cna)
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return;
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/**
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* If bios boot (flash based) -- do not decrement usage count
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*/
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if (bfi_image_get_size(BFA_IOC_FWIMG_TYPE(ioc)) < BFA_IOC_FWIMG_MINSZ)
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return;
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/**
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* decrement usage count
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*/
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bfa_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg);
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usecnt = bfa_reg_read(ioc->ioc_regs.ioc_usage_reg);
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bfa_assert(usecnt > 0);
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usecnt--;
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bfa_reg_write(ioc->ioc_regs.ioc_usage_reg, usecnt);
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bfa_trc(ioc, usecnt);
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bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
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}
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/**
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* Notify other functions on HB failure.
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*/
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static void
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bfa_ioc_ct_notify_hbfail(struct bfa_ioc_s *ioc)
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{
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if (ioc->cna) {
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bfa_reg_write(ioc->ioc_regs.ll_halt, __FW_INIT_HALT_P);
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/* Wait for halt to take effect */
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bfa_reg_read(ioc->ioc_regs.ll_halt);
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} else {
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bfa_reg_write(ioc->ioc_regs.err_set, __PSS_ERR_STATUS_SET);
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bfa_reg_read(ioc->ioc_regs.err_set);
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}
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}
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/**
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* Host to LPU mailbox message addresses
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*/
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static struct { u32 hfn_mbox, lpu_mbox, hfn_pgn; } iocreg_fnreg[] = {
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{ HOSTFN0_LPU_MBOX0_0, LPU_HOSTFN0_MBOX0_0, HOST_PAGE_NUM_FN0 },
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{ HOSTFN1_LPU_MBOX0_8, LPU_HOSTFN1_MBOX0_8, HOST_PAGE_NUM_FN1 },
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{ HOSTFN2_LPU_MBOX0_0, LPU_HOSTFN2_MBOX0_0, HOST_PAGE_NUM_FN2 },
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{ HOSTFN3_LPU_MBOX0_8, LPU_HOSTFN3_MBOX0_8, HOST_PAGE_NUM_FN3 }
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};
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/**
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* Host <-> LPU mailbox command/status registers - port 0
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*/
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static struct { u32 hfn, lpu; } iocreg_mbcmd_p0[] = {
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{ HOSTFN0_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN0_MBOX0_CMD_STAT },
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{ HOSTFN1_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN1_MBOX0_CMD_STAT },
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{ HOSTFN2_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN2_MBOX0_CMD_STAT },
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{ HOSTFN3_LPU0_MBOX0_CMD_STAT, LPU0_HOSTFN3_MBOX0_CMD_STAT }
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};
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/**
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* Host <-> LPU mailbox command/status registers - port 1
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*/
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static struct { u32 hfn, lpu; } iocreg_mbcmd_p1[] = {
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{ HOSTFN0_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN0_MBOX0_CMD_STAT },
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{ HOSTFN1_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN1_MBOX0_CMD_STAT },
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{ HOSTFN2_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN2_MBOX0_CMD_STAT },
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{ HOSTFN3_LPU1_MBOX0_CMD_STAT, LPU1_HOSTFN3_MBOX0_CMD_STAT }
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};
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static void
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bfa_ioc_ct_reg_init(struct bfa_ioc_s *ioc)
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{
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bfa_os_addr_t rb;
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int pcifn = bfa_ioc_pcifn(ioc);
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rb = bfa_ioc_bar0(ioc);
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ioc->ioc_regs.hfn_mbox = rb + iocreg_fnreg[pcifn].hfn_mbox;
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ioc->ioc_regs.lpu_mbox = rb + iocreg_fnreg[pcifn].lpu_mbox;
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ioc->ioc_regs.host_page_num_fn = rb + iocreg_fnreg[pcifn].hfn_pgn;
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if (ioc->port_id == 0) {
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ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG;
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ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG;
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ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd_p0[pcifn].hfn;
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ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd_p0[pcifn].lpu;
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ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0;
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} else {
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ioc->ioc_regs.heartbeat = (rb + BFA_IOC1_HBEAT_REG);
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ioc->ioc_regs.ioc_fwstate = (rb + BFA_IOC1_STATE_REG);
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ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd_p1[pcifn].hfn;
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ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd_p1[pcifn].lpu;
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ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P1;
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}
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/*
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* PSS control registers
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*/
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ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG);
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ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG);
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ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_425_CTL_REG);
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ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_312_CTL_REG);
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/*
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* IOC semaphore registers and serialization
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*/
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ioc->ioc_regs.ioc_sem_reg = (rb + HOST_SEM0_REG);
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ioc->ioc_regs.ioc_usage_sem_reg = (rb + HOST_SEM1_REG);
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ioc->ioc_regs.ioc_init_sem_reg = (rb + HOST_SEM2_REG);
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ioc->ioc_regs.ioc_usage_reg = (rb + BFA_FW_USE_COUNT);
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/**
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* sram memory access
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*/
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ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START);
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ioc->ioc_regs.smem_pg0 = BFI_IOC_SMEM_PG0_CT;
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/*
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* err set reg : for notification of hb failure in fcmode
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*/
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ioc->ioc_regs.err_set = (rb + ERR_SET_REG);
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}
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/**
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* Initialize IOC to port mapping.
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*/
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#define FNC_PERS_FN_SHIFT(__fn) ((__fn) * 8)
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static void
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bfa_ioc_ct_map_port(struct bfa_ioc_s *ioc)
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{
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bfa_os_addr_t rb = ioc->pcidev.pci_bar_kva;
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u32 r32;
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/**
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* For catapult, base port id on personality register and IOC type
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*/
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r32 = bfa_reg_read(rb + FNC_PERS_REG);
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r32 >>= FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc));
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ioc->port_id = (r32 & __F0_PORT_MAP_MK) >> __F0_PORT_MAP_SH;
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bfa_trc(ioc, bfa_ioc_pcifn(ioc));
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bfa_trc(ioc, ioc->port_id);
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}
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/**
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* Set interrupt mode for a function: INTX or MSIX
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*/
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static void
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bfa_ioc_ct_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix)
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{
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bfa_os_addr_t rb = ioc->pcidev.pci_bar_kva;
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u32 r32, mode;
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r32 = bfa_reg_read(rb + FNC_PERS_REG);
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bfa_trc(ioc, r32);
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mode = (r32 >> FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc))) &
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__F0_INTX_STATUS;
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/**
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* If already in desired mode, do not change anything
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*/
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if (!msix && mode)
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return;
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if (msix)
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mode = __F0_INTX_STATUS_MSIX;
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else
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mode = __F0_INTX_STATUS_INTA;
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r32 &= ~(__F0_INTX_STATUS << FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc)));
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r32 |= (mode << FNC_PERS_FN_SHIFT(bfa_ioc_pcifn(ioc)));
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bfa_trc(ioc, r32);
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bfa_reg_write(rb + FNC_PERS_REG, r32);
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}
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static bfa_status_t
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bfa_ioc_ct_pll_init(struct bfa_ioc_s *ioc)
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{
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bfa_os_addr_t rb = ioc->pcidev.pci_bar_kva;
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u32 pll_sclk, pll_fclk, r32;
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/*
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* Hold semaphore so that nobody can access the chip during init.
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*/
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bfa_ioc_sem_get(ioc->ioc_regs.ioc_init_sem_reg);
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pll_sclk = __APP_PLL_312_LRESETN | __APP_PLL_312_ENARST |
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__APP_PLL_312_RSEL200500 | __APP_PLL_312_P0_1(3U) |
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__APP_PLL_312_JITLMT0_1(3U) |
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__APP_PLL_312_CNTLMT0_1(1U);
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pll_fclk = __APP_PLL_425_LRESETN | __APP_PLL_425_ENARST |
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__APP_PLL_425_RSEL200500 | __APP_PLL_425_P0_1(3U) |
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__APP_PLL_425_JITLMT0_1(3U) |
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__APP_PLL_425_CNTLMT0_1(1U);
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/**
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* For catapult, choose operational mode FC/FCoE
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*/
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if (ioc->fcmode) {
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bfa_reg_write((rb + OP_MODE), 0);
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bfa_reg_write((rb + ETH_MAC_SER_REG),
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__APP_EMS_CMLCKSEL |
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__APP_EMS_REFCKBUFEN2 |
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__APP_EMS_CHANNEL_SEL);
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} else {
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ioc->pllinit = BFA_TRUE;
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bfa_reg_write((rb + OP_MODE), __GLOBAL_FCOE_MODE);
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bfa_reg_write((rb + ETH_MAC_SER_REG),
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__APP_EMS_REFCKBUFEN1);
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}
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bfa_reg_write((rb + BFA_IOC0_STATE_REG), BFI_IOC_UNINIT);
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bfa_reg_write((rb + BFA_IOC1_STATE_REG), BFI_IOC_UNINIT);
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bfa_reg_write((rb + HOSTFN0_INT_MSK), 0xffffffffU);
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bfa_reg_write((rb + HOSTFN1_INT_MSK), 0xffffffffU);
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bfa_reg_write((rb + HOSTFN0_INT_STATUS), 0xffffffffU);
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bfa_reg_write((rb + HOSTFN1_INT_STATUS), 0xffffffffU);
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bfa_reg_write((rb + HOSTFN0_INT_MSK), 0xffffffffU);
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bfa_reg_write((rb + HOSTFN1_INT_MSK), 0xffffffffU);
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bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, pll_sclk |
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__APP_PLL_312_LOGIC_SOFT_RESET);
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bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, pll_fclk |
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__APP_PLL_425_LOGIC_SOFT_RESET);
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bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, pll_sclk |
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__APP_PLL_312_LOGIC_SOFT_RESET | __APP_PLL_312_ENABLE);
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bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, pll_fclk |
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__APP_PLL_425_LOGIC_SOFT_RESET | __APP_PLL_425_ENABLE);
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/**
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* Wait for PLLs to lock.
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*/
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bfa_reg_read(rb + HOSTFN0_INT_MSK);
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bfa_os_udelay(2000);
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bfa_reg_write((rb + HOSTFN0_INT_STATUS), 0xffffffffU);
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bfa_reg_write((rb + HOSTFN1_INT_STATUS), 0xffffffffU);
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bfa_reg_write(ioc->ioc_regs.app_pll_slow_ctl_reg, pll_sclk |
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__APP_PLL_312_ENABLE);
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bfa_reg_write(ioc->ioc_regs.app_pll_fast_ctl_reg, pll_fclk |
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__APP_PLL_425_ENABLE);
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/**
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* PSS memory reset is asserted at power-on-reset. Need to clear
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* this before running EDRAM BISTR
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*/
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if (ioc->cna) {
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bfa_reg_write((rb + PMM_1T_RESET_REG_P0), __PMM_1T_RESET_P);
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bfa_reg_write((rb + PMM_1T_RESET_REG_P1), __PMM_1T_RESET_P);
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}
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r32 = bfa_reg_read((rb + PSS_CTL_REG));
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r32 &= ~__PSS_LMEM_RESET;
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bfa_reg_write((rb + PSS_CTL_REG), r32);
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bfa_os_udelay(1000);
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if (ioc->cna) {
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bfa_reg_write((rb + PMM_1T_RESET_REG_P0), 0);
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bfa_reg_write((rb + PMM_1T_RESET_REG_P1), 0);
|
|
}
|
|
|
|
bfa_reg_write((rb + MBIST_CTL_REG), __EDRAM_BISTR_START);
|
|
bfa_os_udelay(1000);
|
|
r32 = bfa_reg_read((rb + MBIST_STAT_REG));
|
|
bfa_trc(ioc, r32);
|
|
|
|
/**
|
|
* Clear BISTR
|
|
*/
|
|
bfa_reg_write((rb + MBIST_CTL_REG), 0);
|
|
|
|
/*
|
|
* release semaphore.
|
|
*/
|
|
bfa_ioc_sem_release(ioc->ioc_regs.ioc_init_sem_reg);
|
|
|
|
return BFA_STATUS_OK;
|
|
}
|
|
|
|
/**
|
|
* Cleanup hw semaphore and usecnt registers
|
|
*/
|
|
static void
|
|
bfa_ioc_ct_ownership_reset(struct bfa_ioc_s *ioc)
|
|
{
|
|
|
|
if (ioc->cna) {
|
|
bfa_ioc_sem_get(ioc->ioc_regs.ioc_usage_sem_reg);
|
|
bfa_reg_write(ioc->ioc_regs.ioc_usage_reg, 0);
|
|
bfa_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
|
|
}
|
|
|
|
/*
|
|
* Read the hw sem reg to make sure that it is locked
|
|
* before we clear it. If it is not locked, writing 1
|
|
* will lock it instead of clearing it.
|
|
*/
|
|
bfa_reg_read(ioc->ioc_regs.ioc_sem_reg);
|
|
bfa_ioc_hw_sem_release(ioc);
|
|
}
|