mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-10-31 09:36:25 +00:00
6443170f6d
This was brought over from UMS, and used for a while until we decided that drm_helper_resume_force_mode was easier and more reliable, since it didn't require duplicating all the code deleted here. We just forgot to delete all that junk for a while.
424 lines
10 KiB
C
424 lines
10 KiB
C
/*
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* Copyright © 2006 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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*
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*/
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#include "dvo.h"
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/*
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* register definitions for the i82807aa.
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*
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* Documentation on this chipset can be found in datasheet #29069001 at
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* intel.com.
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*/
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/*
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* VCH Revision & GMBus Base Addr
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*/
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#define VR00 0x00
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# define VR00_BASE_ADDRESS_MASK 0x007f
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/*
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* Functionality Enable
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*/
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#define VR01 0x01
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/*
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* Enable the panel fitter
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*/
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# define VR01_PANEL_FIT_ENABLE (1 << 3)
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/*
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* Enables the LCD display.
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*
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* This must not be set while VR01_DVO_BYPASS_ENABLE is set.
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*/
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# define VR01_LCD_ENABLE (1 << 2)
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/** Enables the DVO repeater. */
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# define VR01_DVO_BYPASS_ENABLE (1 << 1)
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/** Enables the DVO clock */
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# define VR01_DVO_ENABLE (1 << 0)
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/*
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* LCD Interface Format
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*/
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#define VR10 0x10
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/** Enables LVDS output instead of CMOS */
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# define VR10_LVDS_ENABLE (1 << 4)
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/** Enables 18-bit LVDS output. */
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# define VR10_INTERFACE_1X18 (0 << 2)
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/** Enables 24-bit LVDS or CMOS output */
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# define VR10_INTERFACE_1X24 (1 << 2)
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/** Enables 2x18-bit LVDS or CMOS output. */
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# define VR10_INTERFACE_2X18 (2 << 2)
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/** Enables 2x24-bit LVDS output */
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# define VR10_INTERFACE_2X24 (3 << 2)
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/*
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* VR20 LCD Horizontal Display Size
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*/
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#define VR20 0x20
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/*
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* LCD Vertical Display Size
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*/
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#define VR21 0x20
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/*
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* Panel power down status
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*/
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#define VR30 0x30
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/** Read only bit indicating that the panel is not in a safe poweroff state. */
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# define VR30_PANEL_ON (1 << 15)
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#define VR40 0x40
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# define VR40_STALL_ENABLE (1 << 13)
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# define VR40_VERTICAL_INTERP_ENABLE (1 << 12)
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# define VR40_ENHANCED_PANEL_FITTING (1 << 11)
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# define VR40_HORIZONTAL_INTERP_ENABLE (1 << 10)
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# define VR40_AUTO_RATIO_ENABLE (1 << 9)
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# define VR40_CLOCK_GATING_ENABLE (1 << 8)
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/*
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* Panel Fitting Vertical Ratio
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* (((image_height - 1) << 16) / ((panel_height - 1))) >> 2
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*/
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#define VR41 0x41
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/*
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* Panel Fitting Horizontal Ratio
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* (((image_width - 1) << 16) / ((panel_width - 1))) >> 2
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*/
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#define VR42 0x42
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/*
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* Horizontal Image Size
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*/
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#define VR43 0x43
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/* VR80 GPIO 0
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*/
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#define VR80 0x80
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#define VR81 0x81
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#define VR82 0x82
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#define VR83 0x83
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#define VR84 0x84
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#define VR85 0x85
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#define VR86 0x86
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#define VR87 0x87
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/* VR88 GPIO 8
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*/
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#define VR88 0x88
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/* Graphics BIOS scratch 0
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*/
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#define VR8E 0x8E
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# define VR8E_PANEL_TYPE_MASK (0xf << 0)
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# define VR8E_PANEL_INTERFACE_CMOS (0 << 4)
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# define VR8E_PANEL_INTERFACE_LVDS (1 << 4)
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# define VR8E_FORCE_DEFAULT_PANEL (1 << 5)
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/* Graphics BIOS scratch 1
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*/
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#define VR8F 0x8F
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# define VR8F_VCH_PRESENT (1 << 0)
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# define VR8F_DISPLAY_CONN (1 << 1)
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# define VR8F_POWER_MASK (0x3c)
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# define VR8F_POWER_POS (2)
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struct ivch_priv {
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bool quiet;
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uint16_t width, height;
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};
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static void ivch_dump_regs(struct intel_dvo_device *dvo);
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/**
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* Reads a register on the ivch.
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*
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* Each of the 256 registers are 16 bits long.
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*/
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static bool ivch_read(struct intel_dvo_device *dvo, int addr, uint16_t *data)
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{
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struct ivch_priv *priv = dvo->dev_priv;
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struct i2c_adapter *adapter = dvo->i2c_bus;
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struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
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u8 out_buf[1];
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u8 in_buf[2];
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struct i2c_msg msgs[] = {
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{
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.addr = dvo->slave_addr,
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.flags = I2C_M_RD,
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.len = 0,
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},
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{
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.addr = 0,
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.flags = I2C_M_NOSTART,
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.len = 1,
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.buf = out_buf,
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},
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{
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.addr = dvo->slave_addr,
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.flags = I2C_M_RD | I2C_M_NOSTART,
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.len = 2,
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.buf = in_buf,
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}
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};
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out_buf[0] = addr;
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if (i2c_transfer(&i2cbus->adapter, msgs, 3) == 3) {
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*data = (in_buf[1] << 8) | in_buf[0];
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return true;
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};
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if (!priv->quiet) {
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DRM_DEBUG_KMS("Unable to read register 0x%02x from "
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"%s:%02x.\n",
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addr, i2cbus->adapter.name, dvo->slave_addr);
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}
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return false;
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}
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/** Writes a 16-bit register on the ivch */
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static bool ivch_write(struct intel_dvo_device *dvo, int addr, uint16_t data)
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{
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struct ivch_priv *priv = dvo->dev_priv;
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struct i2c_adapter *adapter = dvo->i2c_bus;
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struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
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u8 out_buf[3];
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struct i2c_msg msg = {
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.addr = dvo->slave_addr,
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.flags = 0,
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.len = 3,
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.buf = out_buf,
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};
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out_buf[0] = addr;
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out_buf[1] = data & 0xff;
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out_buf[2] = data >> 8;
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if (i2c_transfer(&i2cbus->adapter, &msg, 1) == 1)
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return true;
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if (!priv->quiet) {
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DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
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addr, i2cbus->adapter.name, dvo->slave_addr);
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}
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return false;
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}
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/** Probes the given bus and slave address for an ivch */
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static bool ivch_init(struct intel_dvo_device *dvo,
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struct i2c_adapter *adapter)
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{
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struct ivch_priv *priv;
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uint16_t temp;
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priv = kzalloc(sizeof(struct ivch_priv), GFP_KERNEL);
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if (priv == NULL)
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return false;
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dvo->i2c_bus = adapter;
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dvo->dev_priv = priv;
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priv->quiet = true;
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if (!ivch_read(dvo, VR00, &temp))
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goto out;
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priv->quiet = false;
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/* Since the identification bits are probably zeroes, which doesn't seem
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* very unique, check that the value in the base address field matches
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* the address it's responding on.
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*/
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if ((temp & VR00_BASE_ADDRESS_MASK) != dvo->slave_addr) {
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DRM_DEBUG_KMS("ivch detect failed due to address mismatch "
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"(%d vs %d)\n",
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(temp & VR00_BASE_ADDRESS_MASK), dvo->slave_addr);
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goto out;
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}
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ivch_read(dvo, VR20, &priv->width);
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ivch_read(dvo, VR21, &priv->height);
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return true;
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out:
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kfree(priv);
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return false;
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}
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static enum drm_connector_status ivch_detect(struct intel_dvo_device *dvo)
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{
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return connector_status_connected;
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}
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static enum drm_mode_status ivch_mode_valid(struct intel_dvo_device *dvo,
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struct drm_display_mode *mode)
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{
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if (mode->clock > 112000)
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return MODE_CLOCK_HIGH;
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return MODE_OK;
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}
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/** Sets the power state of the panel connected to the ivch */
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static void ivch_dpms(struct intel_dvo_device *dvo, int mode)
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{
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int i;
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uint16_t vr01, vr30, backlight;
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/* Set the new power state of the panel. */
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if (!ivch_read(dvo, VR01, &vr01))
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return;
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if (mode == DRM_MODE_DPMS_ON)
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backlight = 1;
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else
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backlight = 0;
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ivch_write(dvo, VR80, backlight);
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if (mode == DRM_MODE_DPMS_ON)
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vr01 |= VR01_LCD_ENABLE | VR01_DVO_ENABLE;
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else
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vr01 &= ~(VR01_LCD_ENABLE | VR01_DVO_ENABLE);
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ivch_write(dvo, VR01, vr01);
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/* Wait for the panel to make its state transition */
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for (i = 0; i < 100; i++) {
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if (!ivch_read(dvo, VR30, &vr30))
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break;
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if (((vr30 & VR30_PANEL_ON) != 0) == (mode == DRM_MODE_DPMS_ON))
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break;
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udelay(1000);
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}
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/* wait some more; vch may fail to resync sometimes without this */
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udelay(16 * 1000);
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}
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static void ivch_mode_set(struct intel_dvo_device *dvo,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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uint16_t vr40 = 0;
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uint16_t vr01;
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vr01 = 0;
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vr40 = (VR40_STALL_ENABLE | VR40_VERTICAL_INTERP_ENABLE |
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VR40_HORIZONTAL_INTERP_ENABLE);
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if (mode->hdisplay != adjusted_mode->hdisplay ||
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mode->vdisplay != adjusted_mode->vdisplay) {
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uint16_t x_ratio, y_ratio;
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vr01 |= VR01_PANEL_FIT_ENABLE;
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vr40 |= VR40_CLOCK_GATING_ENABLE;
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x_ratio = (((mode->hdisplay - 1) << 16) /
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(adjusted_mode->hdisplay - 1)) >> 2;
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y_ratio = (((mode->vdisplay - 1) << 16) /
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(adjusted_mode->vdisplay - 1)) >> 2;
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ivch_write (dvo, VR42, x_ratio);
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ivch_write (dvo, VR41, y_ratio);
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} else {
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vr01 &= ~VR01_PANEL_FIT_ENABLE;
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vr40 &= ~VR40_CLOCK_GATING_ENABLE;
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}
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vr40 &= ~VR40_AUTO_RATIO_ENABLE;
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ivch_write(dvo, VR01, vr01);
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ivch_write(dvo, VR40, vr40);
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ivch_dump_regs(dvo);
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}
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static void ivch_dump_regs(struct intel_dvo_device *dvo)
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{
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uint16_t val;
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ivch_read(dvo, VR00, &val);
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DRM_LOG_KMS("VR00: 0x%04x\n", val);
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ivch_read(dvo, VR01, &val);
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DRM_LOG_KMS("VR01: 0x%04x\n", val);
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ivch_read(dvo, VR30, &val);
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DRM_LOG_KMS("VR30: 0x%04x\n", val);
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ivch_read(dvo, VR40, &val);
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DRM_LOG_KMS("VR40: 0x%04x\n", val);
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/* GPIO registers */
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ivch_read(dvo, VR80, &val);
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DRM_LOG_KMS("VR80: 0x%04x\n", val);
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ivch_read(dvo, VR81, &val);
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DRM_LOG_KMS("VR81: 0x%04x\n", val);
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ivch_read(dvo, VR82, &val);
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DRM_LOG_KMS("VR82: 0x%04x\n", val);
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ivch_read(dvo, VR83, &val);
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DRM_LOG_KMS("VR83: 0x%04x\n", val);
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ivch_read(dvo, VR84, &val);
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DRM_LOG_KMS("VR84: 0x%04x\n", val);
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ivch_read(dvo, VR85, &val);
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DRM_LOG_KMS("VR85: 0x%04x\n", val);
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ivch_read(dvo, VR86, &val);
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DRM_LOG_KMS("VR86: 0x%04x\n", val);
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ivch_read(dvo, VR87, &val);
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DRM_LOG_KMS("VR87: 0x%04x\n", val);
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ivch_read(dvo, VR88, &val);
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DRM_LOG_KMS("VR88: 0x%04x\n", val);
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/* Scratch register 0 - AIM Panel type */
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ivch_read(dvo, VR8E, &val);
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DRM_LOG_KMS("VR8E: 0x%04x\n", val);
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/* Scratch register 1 - Status register */
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ivch_read(dvo, VR8F, &val);
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DRM_LOG_KMS("VR8F: 0x%04x\n", val);
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}
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static void ivch_destroy(struct intel_dvo_device *dvo)
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{
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struct ivch_priv *priv = dvo->dev_priv;
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if (priv) {
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kfree(priv);
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dvo->dev_priv = NULL;
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}
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}
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struct intel_dvo_dev_ops ivch_ops= {
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.init = ivch_init,
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.dpms = ivch_dpms,
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.mode_valid = ivch_mode_valid,
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.mode_set = ivch_mode_set,
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.detect = ivch_detect,
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.dump_regs = ivch_dump_regs,
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.destroy = ivch_destroy,
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};
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