mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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161 lines
7.5 KiB
C
161 lines
7.5 KiB
C
/* MN10300 on-board serial port module registers
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*
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* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public Licence
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* as published by the Free Software Foundation; either version
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* 2 of the Licence, or (at your option) any later version.
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*/
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#ifndef _ASM_SERIAL_REGS_H
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#define _ASM_SERIAL_REGS_H
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#include <asm/cpu-regs.h>
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#include <asm/intctl-regs.h>
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#ifdef __KERNEL__
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/* serial port 0 */
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#define SC0CTR __SYSREG(0xd4002000, u16) /* control reg */
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#define SC01CTR_CK 0x0007 /* clock source select */
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#define SC0CTR_CK_TM8UFLOW_8 0x0000 /* - 1/8 timer 8 underflow (serial port 0 only) */
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#define SC1CTR_CK_TM9UFLOW_8 0x0000 /* - 1/8 timer 9 underflow (serial port 1 only) */
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#define SC01CTR_CK_IOCLK_8 0x0001 /* - 1/8 IOCLK */
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#define SC01CTR_CK_IOCLK_32 0x0002 /* - 1/32 IOCLK */
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#define SC0CTR_CK_TM2UFLOW_2 0x0003 /* - 1/2 timer 2 underflow (serial port 0 only) */
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#define SC1CTR_CK_TM3UFLOW_2 0x0003 /* - 1/2 timer 3 underflow (serial port 1 only) */
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#define SC0CTR_CK_TM0UFLOW_8 0x0004 /* - 1/8 timer 1 underflow (serial port 0 only) */
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#define SC1CTR_CK_TM1UFLOW_8 0x0004 /* - 1/8 timer 2 underflow (serial port 1 only) */
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#define SC0CTR_CK_TM2UFLOW_8 0x0005 /* - 1/8 timer 2 underflow (serial port 0 only) */
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#define SC1CTR_CK_TM3UFLOW_8 0x0005 /* - 1/8 timer 3 underflow (serial port 1 only) */
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#define SC01CTR_CK_EXTERN_8 0x0006 /* - 1/8 external closk */
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#define SC01CTR_CK_EXTERN 0x0007 /* - external closk */
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#define SC01CTR_STB 0x0008 /* stop bit select */
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#define SC01CTR_STB_1BIT 0x0000 /* - 1 stop bit */
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#define SC01CTR_STB_2BIT 0x0008 /* - 2 stop bits */
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#define SC01CTR_PB 0x0070 /* parity bit select */
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#define SC01CTR_PB_NONE 0x0000 /* - no parity */
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#define SC01CTR_PB_FIXED0 0x0040 /* - fixed at 0 */
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#define SC01CTR_PB_FIXED1 0x0050 /* - fixed at 1 */
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#define SC01CTR_PB_EVEN 0x0060 /* - even parity */
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#define SC01CTR_PB_ODD 0x0070 /* - odd parity */
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#define SC01CTR_CLN 0x0080 /* character length */
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#define SC01CTR_CLN_7BIT 0x0000 /* - 7 bit chars */
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#define SC01CTR_CLN_8BIT 0x0080 /* - 8 bit chars */
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#define SC01CTR_TOE 0x0100 /* T input output enable */
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#define SC01CTR_OD 0x0200 /* bit order select */
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#define SC01CTR_OD_LSBFIRST 0x0000 /* - LSB first */
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#define SC01CTR_OD_MSBFIRST 0x0200 /* - MSB first */
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#define SC01CTR_MD 0x0c00 /* mode select */
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#define SC01CTR_MD_STST_SYNC 0x0000 /* - start-stop synchronous */
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#define SC01CTR_MD_CLOCK_SYNC1 0x0400 /* - clock synchronous 1 */
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#define SC01CTR_MD_I2C 0x0800 /* - I2C mode */
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#define SC01CTR_MD_CLOCK_SYNC2 0x0c00 /* - clock synchronous 2 */
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#define SC01CTR_IIC 0x1000 /* I2C mode select */
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#define SC01CTR_BKE 0x2000 /* break transmit enable */
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#define SC01CTR_RXE 0x4000 /* receive enable */
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#define SC01CTR_TXE 0x8000 /* transmit enable */
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#define SC0ICR __SYSREG(0xd4002004, u8) /* interrupt control reg */
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#define SC01ICR_DMD 0x80 /* output data mode */
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#define SC01ICR_TD 0x20 /* transmit DMA trigger cause */
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#define SC01ICR_TI 0x10 /* transmit interrupt cause */
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#define SC01ICR_RES 0x04 /* receive error select */
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#define SC01ICR_RI 0x01 /* receive interrupt cause */
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#define SC0TXB __SYSREG(0xd4002008, u8) /* transmit buffer reg */
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#define SC0RXB __SYSREG(0xd4002009, u8) /* receive buffer reg */
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#define SC0STR __SYSREG(0xd400200c, u16) /* status reg */
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#define SC01STR_OEF 0x0001 /* overrun error found */
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#define SC01STR_PEF 0x0002 /* parity error found */
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#define SC01STR_FEF 0x0004 /* framing error found */
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#define SC01STR_RBF 0x0010 /* receive buffer status */
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#define SC01STR_TBF 0x0020 /* transmit buffer status */
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#define SC01STR_RXF 0x0040 /* receive status */
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#define SC01STR_TXF 0x0080 /* transmit status */
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#define SC01STR_STF 0x0100 /* I2C start sequence found */
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#define SC01STR_SPF 0x0200 /* I2C stop sequence found */
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#define SC0RXIRQ 20 /* timer 0 Receive IRQ */
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#define SC0TXIRQ 21 /* timer 0 Transmit IRQ */
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#define SC0RXICR GxICR(SC0RXIRQ) /* serial 0 receive intr ctrl reg */
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#define SC0TXICR GxICR(SC0TXIRQ) /* serial 0 transmit intr ctrl reg */
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/* serial port 1 */
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#define SC1CTR __SYSREG(0xd4002010, u16) /* serial port 1 control */
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#define SC1ICR __SYSREG(0xd4002014, u8) /* interrupt control reg */
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#define SC1TXB __SYSREG(0xd4002018, u8) /* transmit buffer reg */
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#define SC1RXB __SYSREG(0xd4002019, u8) /* receive buffer reg */
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#define SC1STR __SYSREG(0xd400201c, u16) /* status reg */
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#define SC1RXIRQ 22 /* timer 1 Receive IRQ */
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#define SC1TXIRQ 23 /* timer 1 Transmit IRQ */
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#define SC1RXICR GxICR(SC1RXIRQ) /* serial 1 receive intr ctrl reg */
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#define SC1TXICR GxICR(SC1TXIRQ) /* serial 1 transmit intr ctrl reg */
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/* serial port 2 */
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#define SC2CTR __SYSREG(0xd4002020, u16) /* control reg */
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#define SC2CTR_CK 0x0003 /* clock source select */
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#define SC2CTR_CK_TM10UFLOW 0x0000 /* - timer 10 underflow */
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#define SC2CTR_CK_TM2UFLOW 0x0001 /* - timer 2 underflow */
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#define SC2CTR_CK_EXTERN 0x0002 /* - external closk */
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#define SC2CTR_CK_TM3UFLOW 0x0003 /* - timer 3 underflow */
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#define SC2CTR_STB 0x0008 /* stop bit select */
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#define SC2CTR_STB_1BIT 0x0000 /* - 1 stop bit */
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#define SC2CTR_STB_2BIT 0x0008 /* - 2 stop bits */
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#define SC2CTR_PB 0x0070 /* parity bit select */
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#define SC2CTR_PB_NONE 0x0000 /* - no parity */
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#define SC2CTR_PB_FIXED0 0x0040 /* - fixed at 0 */
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#define SC2CTR_PB_FIXED1 0x0050 /* - fixed at 1 */
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#define SC2CTR_PB_EVEN 0x0060 /* - even parity */
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#define SC2CTR_PB_ODD 0x0070 /* - odd parity */
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#define SC2CTR_CLN 0x0080 /* character length */
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#define SC2CTR_CLN_7BIT 0x0000 /* - 7 bit chars */
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#define SC2CTR_CLN_8BIT 0x0080 /* - 8 bit chars */
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#define SC2CTR_TWE 0x0100 /* transmit wait enable (enable XCTS control) */
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#define SC2CTR_OD 0x0200 /* bit order select */
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#define SC2CTR_OD_LSBFIRST 0x0000 /* - LSB first */
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#define SC2CTR_OD_MSBFIRST 0x0200 /* - MSB first */
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#define SC2CTR_TWS 0x1000 /* transmit wait select */
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#define SC2CTR_TWS_XCTS_HIGH 0x0000 /* - interrupt TX when XCTS high */
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#define SC2CTR_TWS_XCTS_LOW 0x1000 /* - interrupt TX when XCTS low */
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#define SC2CTR_BKE 0x2000 /* break transmit enable */
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#define SC2CTR_RXE 0x4000 /* receive enable */
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#define SC2CTR_TXE 0x8000 /* transmit enable */
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#define SC2ICR __SYSREG(0xd4002024, u8) /* interrupt control reg */
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#define SC2ICR_TD 0x20 /* transmit DMA trigger cause */
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#define SC2ICR_TI 0x10 /* transmit interrupt cause */
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#define SC2ICR_RES 0x04 /* receive error select */
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#define SC2ICR_RI 0x01 /* receive interrupt cause */
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#define SC2TXB __SYSREG(0xd4002018, u8) /* transmit buffer reg */
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#define SC2RXB __SYSREG(0xd4002019, u8) /* receive buffer reg */
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#define SC2STR __SYSREG(0xd400201c, u8) /* status reg */
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#define SC2STR_OEF 0x0001 /* overrun error found */
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#define SC2STR_PEF 0x0002 /* parity error found */
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#define SC2STR_FEF 0x0004 /* framing error found */
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#define SC2STR_CTS 0x0008 /* XCTS input pin status (0 means high) */
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#define SC2STR_RBF 0x0010 /* receive buffer status */
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#define SC2STR_TBF 0x0020 /* transmit buffer status */
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#define SC2STR_RXF 0x0040 /* receive status */
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#define SC2STR_TXF 0x0080 /* transmit status */
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#define SC2TIM __SYSREG(0xd400202d, u8) /* status reg */
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#define SC2RXIRQ 24 /* serial 2 Receive IRQ */
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#define SC2TXIRQ 25 /* serial 2 Transmit IRQ */
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#define SC2RXICR GxICR(SC2RXIRQ) /* serial 2 receive intr ctrl reg */
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#define SC2TXICR GxICR(SC2TXIRQ) /* serial 2 transmit intr ctrl reg */
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#endif /* __KERNEL__ */
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#endif /* _ASM_SERIAL_REGS_H */
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