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	 a003708ad4
			
		
	
	
		a003708ad4
		
	
	
	
	
		
			
			Freescale i.MX51 processor uses a new interrupt controller. Add driver for TrustZone Interrupt Controller Signed-off-by: Amit Kucheria <amit.kucheria@canonical.com>
		
			
				
	
	
		
			85 lines
		
	
	
		
			2.0 KiB
		
	
	
	
		
			ArmAsm
		
	
	
	
	
	
			
		
		
	
	
			85 lines
		
	
	
		
			2.0 KiB
		
	
	
	
		
			ArmAsm
		
	
	
	
	
	
| /*
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|  *  Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
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|  *  Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
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|  */
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| 
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| /*
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|  * This program is free software; you can redistribute it and/or modify
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|  * it under the terms of the GNU General Public License version 2 as
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|  * published by the Free Software Foundation.
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|  */
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| 
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| #include <mach/hardware.h>
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| 
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| #define AVIC_NIMASK	0x04
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| 
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| 	@ this macro disables fast irq (not implemented)
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| 	.macro	disable_fiq
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| 	.endm
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| 
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| 	.macro  get_irqnr_preamble, base, tmp
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| #ifndef CONFIG_MXC_TZIC
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| 	ldr	\base, =avic_base
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| 	ldr	\base, [\base]
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| #ifdef CONFIG_MXC_IRQ_PRIOR
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| 	ldr	r4, [\base, #AVIC_NIMASK]
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| #endif
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| #elif defined CONFIG_MXC_TZIC
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| 	ldr	\base, =tzic_base
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| 	ldr	\base, [\base]
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| #endif /* CONFIG_MXC_TZIC */
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| 	.endm
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| 
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| 	.macro  arch_ret_to_user, tmp1, tmp2
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| 	.endm
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| 
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| 	@ this macro checks which interrupt occured
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| 	@ and returns its number in irqnr
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| 	@ and returns if an interrupt occured in irqstat
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| 	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
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| #ifndef CONFIG_MXC_TZIC
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| 	@ Load offset & priority of the highest priority
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| 	@ interrupt pending from AVIC_NIVECSR
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| 	ldr	\irqstat, [\base, #0x40]
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| 	@ Shift to get the decoded IRQ number, using ASR so
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| 	@ 'no interrupt pending' becomes 0xffffffff
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| 	mov	\irqnr, \irqstat, asr #16
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| 	@ set zero flag if IRQ + 1 == 0
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| 	adds	\tmp, \irqnr, #1
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| #ifdef CONFIG_MXC_IRQ_PRIOR
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| 	bicne	\tmp, \irqstat, #0xFFFFFFE0
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| 	strne	\tmp, [\base, #AVIC_NIMASK]
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| 	streq	r4, [\base, #AVIC_NIMASK]
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| #endif
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| #elif defined CONFIG_MXC_TZIC
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| 	@ Load offset & priority of the highest priority
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| 	@ interrupt pending.
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| 	@ 0xD80 is HIPND0 register
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| 	mov     \irqnr, #0
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| 	mov     \irqstat, #0x0D80
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| 1000:
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| 	ldr     \tmp,   [\irqstat, \base]
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| 	cmp     \tmp, #0
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| 	bne     1001f
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| 	addeq   \irqnr, \irqnr, #32
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| 	addeq   \irqstat, \irqstat, #4
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| 	cmp     \irqnr, #128
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| 	blo     1000b
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| 	b       2001f
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| 1001:	mov     \irqstat, #1
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| 1002:	tst     \tmp, \irqstat
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| 	bne     2002f
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| 	movs    \tmp, \tmp, lsr #1
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| 	addne   \irqnr, \irqnr, #1
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| 	bne     1002b
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| 2001:
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| 	mov  \irqnr, #0
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| 2002:
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| 	movs \irqnr, \irqnr
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| #endif
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| 	.endm
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| 
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| 	@ irq priority table (not used)
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| 	.macro	irq_prio_table
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| 	.endm
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