mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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1a4a561bdd
add csp dmac header files Signed-off-by: Leo Chen <leochen@broadcom.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
597 lines
24 KiB
C
597 lines
24 KiB
C
/*****************************************************************************
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* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2, available at
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* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a
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* license other than the GPL, without Broadcom's express prior written
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* consent.
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*****************************************************************************/
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/****************************************************************************/
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/**
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* @file dmacHw.h
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*
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* @brief API definitions for low level DMA controller driver
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*
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*/
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/****************************************************************************/
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#ifndef _DMACHW_H
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#define _DMACHW_H
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#include <stddef.h>
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#include <csp/stdint.h>
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#include <mach/csp/dmacHw_reg.h>
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/* Define DMA Channel ID using DMA controller number (m) and channel number (c).
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System specific channel ID should be defined as follows
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For example:
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#include <dmacHw.h>
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...
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#define systemHw_LCD_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,5)
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#define systemHw_SWITCH_RX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,0)
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#define systemHw_SWITCH_TX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,1)
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#define systemHw_APM_RX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,3)
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#define systemHw_APM_TX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,4)
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...
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#define systemHw_SHARED1_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(1,4)
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#define systemHw_SHARED2_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(1,5)
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#define systemHw_SHARED3_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,6)
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...
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*/
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#define dmacHw_MAKE_CHANNEL_ID(m, c) (m << 8 | c)
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typedef enum {
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dmacHw_CHANNEL_PRIORITY_0 = dmacHw_REG_CFG_LO_CH_PRIORITY_0, /* Channel priority 0. Lowest priority DMA channel */
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dmacHw_CHANNEL_PRIORITY_1 = dmacHw_REG_CFG_LO_CH_PRIORITY_1, /* Channel priority 1 */
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dmacHw_CHANNEL_PRIORITY_2 = dmacHw_REG_CFG_LO_CH_PRIORITY_2, /* Channel priority 2 */
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dmacHw_CHANNEL_PRIORITY_3 = dmacHw_REG_CFG_LO_CH_PRIORITY_3, /* Channel priority 3 */
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dmacHw_CHANNEL_PRIORITY_4 = dmacHw_REG_CFG_LO_CH_PRIORITY_4, /* Channel priority 4 */
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dmacHw_CHANNEL_PRIORITY_5 = dmacHw_REG_CFG_LO_CH_PRIORITY_5, /* Channel priority 5 */
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dmacHw_CHANNEL_PRIORITY_6 = dmacHw_REG_CFG_LO_CH_PRIORITY_6, /* Channel priority 6 */
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dmacHw_CHANNEL_PRIORITY_7 = dmacHw_REG_CFG_LO_CH_PRIORITY_7 /* Channel priority 7. Highest priority DMA channel */
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} dmacHw_CHANNEL_PRIORITY_e;
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/* Source destination master interface */
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typedef enum {
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dmacHw_SRC_MASTER_INTERFACE_1 = dmacHw_REG_CTL_SMS_1, /* Source DMA master interface 1 */
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dmacHw_SRC_MASTER_INTERFACE_2 = dmacHw_REG_CTL_SMS_2, /* Source DMA master interface 2 */
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dmacHw_DST_MASTER_INTERFACE_1 = dmacHw_REG_CTL_DMS_1, /* Destination DMA master interface 1 */
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dmacHw_DST_MASTER_INTERFACE_2 = dmacHw_REG_CTL_DMS_2 /* Destination DMA master interface 2 */
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} dmacHw_MASTER_INTERFACE_e;
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typedef enum {
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dmacHw_SRC_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_SRC_TR_WIDTH_8, /* Source 8 bit (1 byte) per transaction */
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dmacHw_SRC_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_SRC_TR_WIDTH_16, /* Source 16 bit (2 byte) per transaction */
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dmacHw_SRC_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_SRC_TR_WIDTH_32, /* Source 32 bit (4 byte) per transaction */
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dmacHw_SRC_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_SRC_TR_WIDTH_64, /* Source 64 bit (8 byte) per transaction */
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dmacHw_DST_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_DST_TR_WIDTH_8, /* Destination 8 bit (1 byte) per transaction */
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dmacHw_DST_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_DST_TR_WIDTH_16, /* Destination 16 bit (2 byte) per transaction */
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dmacHw_DST_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_DST_TR_WIDTH_32, /* Destination 32 bit (4 byte) per transaction */
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dmacHw_DST_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_DST_TR_WIDTH_64 /* Destination 64 bit (8 byte) per transaction */
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} dmacHw_TRANSACTION_WIDTH_e;
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typedef enum {
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dmacHw_SRC_BURST_WIDTH_0 = dmacHw_REG_CTL_SRC_MSIZE_0, /* Source No burst */
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dmacHw_SRC_BURST_WIDTH_4 = dmacHw_REG_CTL_SRC_MSIZE_4, /* Source 4 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
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dmacHw_SRC_BURST_WIDTH_8 = dmacHw_REG_CTL_SRC_MSIZE_8, /* Source 8 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
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dmacHw_SRC_BURST_WIDTH_16 = dmacHw_REG_CTL_SRC_MSIZE_16, /* Source 16 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
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dmacHw_DST_BURST_WIDTH_0 = dmacHw_REG_CTL_DST_MSIZE_0, /* Destination No burst */
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dmacHw_DST_BURST_WIDTH_4 = dmacHw_REG_CTL_DST_MSIZE_4, /* Destination 4 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
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dmacHw_DST_BURST_WIDTH_8 = dmacHw_REG_CTL_DST_MSIZE_8, /* Destination 8 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
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dmacHw_DST_BURST_WIDTH_16 = dmacHw_REG_CTL_DST_MSIZE_16 /* Destination 16 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
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} dmacHw_BURST_WIDTH_e;
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typedef enum {
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dmacHw_TRANSFER_TYPE_MEM_TO_MEM = dmacHw_REG_CTL_TTFC_MM_DMAC, /* Memory to memory transfer */
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dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM = dmacHw_REG_CTL_TTFC_PM_DMAC, /* Peripheral to memory transfer */
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dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_MP_DMAC, /* Memory to peripheral transfer */
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dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_PP_DMAC /* Peripheral to peripheral transfer */
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} dmacHw_TRANSFER_TYPE_e;
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typedef enum {
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dmacHw_TRANSFER_MODE_PERREQUEST, /* Block transfer per DMA request */
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dmacHw_TRANSFER_MODE_CONTINUOUS, /* Continuous transfer of streaming data */
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dmacHw_TRANSFER_MODE_PERIODIC /* Periodic transfer of streaming data */
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} dmacHw_TRANSFER_MODE_e;
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typedef enum {
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dmacHw_SRC_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_SINC_INC, /* Increment source address after every transaction */
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dmacHw_SRC_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_SINC_DEC, /* Decrement source address after every transaction */
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dmacHw_DST_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_DINC_INC, /* Increment destination address after every transaction */
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dmacHw_DST_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_DINC_DEC, /* Decrement destination address after every transaction */
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dmacHw_SRC_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_SINC_NC, /* No change in source address after every transaction */
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dmacHw_DST_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_DINC_NC /* No change in destination address after every transaction */
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} dmacHw_ADDRESS_UPDATE_MODE_e;
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typedef enum {
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dmacHw_FLOW_CONTROL_DMA, /* DMA working as flow controller (default) */
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dmacHw_FLOW_CONTROL_PERIPHERAL /* Peripheral working as flow controller */
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} dmacHw_FLOW_CONTROL_e;
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typedef enum {
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dmacHw_TRANSFER_STATUS_BUSY, /* DMA Transfer ongoing */
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dmacHw_TRANSFER_STATUS_DONE, /* DMA Transfer completed */
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dmacHw_TRANSFER_STATUS_ERROR /* DMA Transfer error */
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} dmacHw_TRANSFER_STATUS_e;
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typedef enum {
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dmacHw_INTERRUPT_DISABLE, /* Interrupt disable */
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dmacHw_INTERRUPT_ENABLE /* Interrupt enable */
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} dmacHw_INTERRUPT_e;
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typedef enum {
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dmacHw_INTERRUPT_STATUS_NONE = 0x0, /* No DMA interrupt */
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dmacHw_INTERRUPT_STATUS_TRANS = 0x1, /* End of DMA transfer interrupt */
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dmacHw_INTERRUPT_STATUS_BLOCK = 0x2, /* End of block transfer interrupt */
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dmacHw_INTERRUPT_STATUS_ERROR = 0x4 /* Error interrupt */
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} dmacHw_INTERRUPT_STATUS_e;
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typedef enum {
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dmacHw_CONTROLLER_ATTRIB_CHANNEL_NUM, /* Number of DMA channel */
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dmacHw_CONTROLLER_ATTRIB_CHANNEL_MAX_BLOCK_SIZE, /* Maximum channel burst size */
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dmacHw_CONTROLLER_ATTRIB_MASTER_INTF_NUM, /* Number of DMA master interface */
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dmacHw_CONTROLLER_ATTRIB_CHANNEL_BUS_WIDTH, /* Channel Data bus width */
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dmacHw_CONTROLLER_ATTRIB_CHANNEL_FIFO_SIZE /* Channel FIFO size */
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} dmacHw_CONTROLLER_ATTRIB_e;
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typedef unsigned long dmacHw_HANDLE_t; /* DMA channel handle */
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typedef uint32_t dmacHw_ID_t; /* DMA channel Id. Must be created using
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"dmacHw_MAKE_CHANNEL_ID" macro
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*/
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/* DMA channel configuration parameters */
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typedef struct {
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uint32_t srcPeripheralPort; /* Source peripheral port */
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uint32_t dstPeripheralPort; /* Destination peripheral port */
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uint32_t srcStatusRegisterAddress; /* Source status register address */
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uint32_t dstStatusRegisterAddress; /* Destination status register address of type */
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uint32_t srcGatherWidth; /* Number of bytes gathered before successive gather opearation */
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uint32_t srcGatherJump; /* Number of bytes jumpped before successive gather opearation */
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uint32_t dstScatterWidth; /* Number of bytes sacattered before successive scatter opearation */
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uint32_t dstScatterJump; /* Number of bytes jumpped before successive scatter opearation */
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uint32_t maxDataPerBlock; /* Maximum number of bytes to be transferred per block/descrptor.
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0 = Maximum possible.
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*/
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dmacHw_ADDRESS_UPDATE_MODE_e srcUpdate; /* Source address update mode */
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dmacHw_ADDRESS_UPDATE_MODE_e dstUpdate; /* Destination address update mode */
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dmacHw_TRANSFER_TYPE_e transferType; /* DMA transfer type */
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dmacHw_TRANSFER_MODE_e transferMode; /* DMA transfer mode */
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dmacHw_MASTER_INTERFACE_e srcMasterInterface; /* DMA source interface */
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dmacHw_MASTER_INTERFACE_e dstMasterInterface; /* DMA destination interface */
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dmacHw_TRANSACTION_WIDTH_e srcMaxTransactionWidth; /* Source transaction width */
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dmacHw_TRANSACTION_WIDTH_e dstMaxTransactionWidth; /* Destination transaction width */
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dmacHw_BURST_WIDTH_e srcMaxBurstWidth; /* Source burst width */
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dmacHw_BURST_WIDTH_e dstMaxBurstWidth; /* Destination burst width */
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dmacHw_INTERRUPT_e blockTransferInterrupt; /* Block trsnafer interrupt */
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dmacHw_INTERRUPT_e completeTransferInterrupt; /* Complete DMA trsnafer interrupt */
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dmacHw_INTERRUPT_e errorInterrupt; /* Error interrupt */
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dmacHw_CHANNEL_PRIORITY_e channelPriority; /* Channel priority */
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dmacHw_FLOW_CONTROL_e flowControler; /* Data flow controller */
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} dmacHw_CONFIG_t;
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/****************************************************************************/
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/**
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* @brief Initializes DMA
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*
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* This function initializes DMA CSP driver
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*
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* @note
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* Must be called before using any DMA channel
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*/
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/****************************************************************************/
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void dmacHw_initDma(void);
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/****************************************************************************/
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/**
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* @brief Exit function for DMA
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*
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* This function isolates DMA from the system
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*
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*/
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/****************************************************************************/
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void dmacHw_exitDma(void);
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/****************************************************************************/
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/**
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* @brief Gets a handle to a DMA channel
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*
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* This function returns a handle, representing a control block of a particular DMA channel
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*
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* @return -1 - On Failure
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* handle - On Success, representing a channel control block
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*
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* @note
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* None Channel ID must be created using "dmacHw_MAKE_CHANNEL_ID" macro
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*/
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/****************************************************************************/
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dmacHw_HANDLE_t dmacHw_getChannelHandle(dmacHw_ID_t channelId /* [ IN ] DMA Channel Id */
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);
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/****************************************************************************/
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/**
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* @brief Initializes a DMA channel for use
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*
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* This function initializes and resets a DMA channel for use
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*
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* @return -1 - On Failure
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* 0 - On Success
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*
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* @note
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* None
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*/
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/****************************************************************************/
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int dmacHw_initChannel(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
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);
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/****************************************************************************/
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/**
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* @brief Estimates number of descriptor needed to perform certain DMA transfer
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*
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*
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* @return On failure : -1
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* On success : Number of descriptor count
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*
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*
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*/
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/****************************************************************************/
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int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
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void *pSrcAddr, /* [ IN ] Source (Peripheral/Memory) address */
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void *pDstAddr, /* [ IN ] Destination (Peripheral/Memory) address */
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size_t dataLen /* [ IN ] Data length in bytes */
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);
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/****************************************************************************/
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/**
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* @brief Initializes descriptor ring
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*
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* This function will initializes the descriptor ring of a DMA channel
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*
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*
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* @return -1 - On failure
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* 0 - On success
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* @note
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* - "len" parameter should be obtained from "dmacHw_descriptorLen"
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* - Descriptor buffer MUST be 32 bit aligned and uncached as it
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* is accessed by ARM and DMA
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*/
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/****************************************************************************/
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int dmacHw_initDescriptor(void *pDescriptorVirt, /* [ IN ] Virtual address of uncahced buffer allocated to form descriptor ring */
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uint32_t descriptorPhyAddr, /* [ IN ] Physical address of pDescriptorVirt (descriptor buffer) */
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uint32_t len, /* [ IN ] Size of the pBuf */
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uint32_t num /* [ IN ] Number of descriptor in the ring */
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);
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/****************************************************************************/
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/**
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* @brief Finds amount of memory required to form a descriptor ring
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*
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*
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* @return Number of bytes required to form a descriptor ring
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*
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*
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* @note
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* None
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*/
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/****************************************************************************/
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uint32_t dmacHw_descriptorLen(uint32_t descCnt /* [ IN ] Number of descriptor in the ring */
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);
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/****************************************************************************/
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/**
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* @brief Configure DMA channel
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*
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* @return 0 : On success
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* -1 : On failure
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*/
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/****************************************************************************/
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int dmacHw_configChannel(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
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dmacHw_CONFIG_t *pConfig /* [ IN ] Configuration settings */
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);
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/****************************************************************************/
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/**
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* @brief Set descriptors for known data length
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*
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* When DMA has to work as a flow controller, this function prepares the
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* descriptor chain to transfer data
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*
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* from:
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* - Memory to memory
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* - Peripheral to memory
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* - Memory to Peripheral
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* - Peripheral to Peripheral
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*
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* @return -1 - On failure
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* 0 - On success
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*
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*/
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/****************************************************************************/
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int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
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void *pDescriptor, /* [ IN ] Descriptor buffer */
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void *pSrcAddr, /* [ IN ] Source (Peripheral/Memory) address */
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void *pDstAddr, /* [ IN ] Destination (Peripheral/Memory) address */
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size_t dataLen /* [ IN ] Length in bytes */
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);
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/****************************************************************************/
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/**
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* @brief Indicates whether DMA transfer is in progress or completed
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*
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* @return DMA transfer status
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* dmacHw_TRANSFER_STATUS_BUSY: DMA Transfer ongoing
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* dmacHw_TRANSFER_STATUS_DONE: DMA Transfer completed
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* dmacHw_TRANSFER_STATUS_ERROR: DMA Transfer error
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*
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*/
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/****************************************************************************/
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dmacHw_TRANSFER_STATUS_e dmacHw_transferCompleted(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
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);
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/****************************************************************************/
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/**
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* @brief Set descriptor carrying control information
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*
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* This function will be used to send specific control information to the device
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* using the DMA channel
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*
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*
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* @return -1 - On failure
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* 0 - On success
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*
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* @note
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* None
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*/
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/****************************************************************************/
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int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
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void *pDescriptor, /* [ IN ] Descriptor buffer */
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uint32_t ctlAddress, /* [ IN ] Address of the device control register */
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uint32_t control /* [ IN ] Device control information */
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);
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/****************************************************************************/
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/**
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* @brief Read data DMA transferred to memory
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*
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* This function will read data that has been DMAed to memory while transfering from:
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* - Memory to memory
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* - Peripheral to memory
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*
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* @return 0 - No more data is available to read
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* 1 - More data might be available to read
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*
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*/
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/****************************************************************************/
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int dmacHw_readTransferredData(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
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dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
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void *pDescriptor, /* [ IN ] Descriptor buffer */
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void **ppBbuf, /* [ OUT ] Data received */
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size_t *pLlen /* [ OUT ] Length of the data received */
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);
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/****************************************************************************/
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/**
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* @brief Prepares descriptor ring, when source peripheral working as a flow controller
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*
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* This function will form the descriptor ring by allocating buffers, when source peripheral
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* has to work as a flow controller to transfer data from:
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* - Peripheral to memory.
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*
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* @return -1 - On failure
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* 0 - On success
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*
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*
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* @note
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* None
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*/
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/****************************************************************************/
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int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
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dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
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void *pDescriptor, /* [ IN ] Descriptor buffer */
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uint32_t srcAddr, /* [ IN ] Source peripheral address */
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void *(*fpAlloc) (int len), /* [ IN ] Function pointer that provides destination memory */
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int len, /* [ IN ] Number of bytes "fpAlloc" will allocate for destination */
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int num /* [ IN ] Number of descriptor to set */
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);
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/****************************************************************************/
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/**
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* @brief Program channel register to initiate transfer
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*
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* @return void
|
|
*
|
|
*
|
|
* @note
|
|
* - Descriptor buffer MUST ALWAYS be flushed before calling this function
|
|
* - This function should also be called from ISR to program the channel with
|
|
* pending descriptors
|
|
*/
|
|
/****************************************************************************/
|
|
void dmacHw_initiateTransfer(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
|
|
dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
|
|
void *pDescriptor /* [ IN ] Descriptor buffer */
|
|
);
|
|
|
|
/****************************************************************************/
|
|
/**
|
|
* @brief Resets descriptor control information
|
|
*
|
|
* @return void
|
|
*/
|
|
/****************************************************************************/
|
|
void dmacHw_resetDescriptorControl(void *pDescriptor /* [ IN ] Descriptor buffer */
|
|
);
|
|
|
|
/****************************************************************************/
|
|
/**
|
|
* @brief Program channel register to stop transfer
|
|
*
|
|
* Ensures the channel is not doing any transfer after calling this function
|
|
*
|
|
* @return void
|
|
*
|
|
*/
|
|
/****************************************************************************/
|
|
void dmacHw_stopTransfer(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
|
|
);
|
|
|
|
/****************************************************************************/
|
|
/**
|
|
* @brief Check the existance of pending descriptor
|
|
*
|
|
* This function confirmes if there is any pending descriptor in the chain
|
|
* to program the channel
|
|
*
|
|
* @return 1 : Channel need to be programmed with pending descriptor
|
|
* 0 : No more pending descriptor to programe the channel
|
|
*
|
|
* @note
|
|
* - This function should be called from ISR in case there are pending
|
|
* descriptor to program the channel.
|
|
*
|
|
* Example:
|
|
*
|
|
* dmac_isr ()
|
|
* {
|
|
* ...
|
|
* if (dmacHw_descriptorPending (handle))
|
|
* {
|
|
* dmacHw_initiateTransfer (handle);
|
|
* }
|
|
* }
|
|
*
|
|
*/
|
|
/****************************************************************************/
|
|
uint32_t dmacHw_descriptorPending(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
|
|
void *pDescriptor /* [ IN ] Descriptor buffer */
|
|
);
|
|
|
|
/****************************************************************************/
|
|
/**
|
|
* @brief Deallocates source or destination memory, allocated
|
|
*
|
|
* This function can be called to deallocate data memory that was DMAed successfully
|
|
*
|
|
* @return -1 - On failure
|
|
* 0 - On success
|
|
*
|
|
* @note
|
|
* This function will be called ONLY, when source OR destination address is pointing
|
|
* to dynamic memory
|
|
*/
|
|
/****************************************************************************/
|
|
int dmacHw_freeMem(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */
|
|
void *pDescriptor, /* [ IN ] Descriptor buffer */
|
|
void (*fpFree) (void *) /* [ IN ] Function pointer to free data memory */
|
|
);
|
|
|
|
/****************************************************************************/
|
|
/**
|
|
* @brief Clears the interrupt
|
|
*
|
|
* This function clears the DMA channel specific interrupt
|
|
*
|
|
* @return N/A
|
|
*
|
|
* @note
|
|
* Must be called under the context of ISR
|
|
*/
|
|
/****************************************************************************/
|
|
void dmacHw_clearInterrupt(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
|
|
);
|
|
|
|
/****************************************************************************/
|
|
/**
|
|
* @brief Returns the cause of channel specific DMA interrupt
|
|
*
|
|
* This function returns the cause of interrupt
|
|
*
|
|
* @return Interrupt status, each bit representing a specific type of interrupt
|
|
* of type dmacHw_INTERRUPT_STATUS_e
|
|
* @note
|
|
* This function should be called under the context of ISR
|
|
*/
|
|
/****************************************************************************/
|
|
dmacHw_INTERRUPT_STATUS_e dmacHw_getInterruptStatus(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
|
|
);
|
|
|
|
/****************************************************************************/
|
|
/**
|
|
* @brief Indentifies a DMA channel causing interrupt
|
|
*
|
|
* This functions returns a channel causing interrupt of type dmacHw_INTERRUPT_STATUS_e
|
|
*
|
|
* @return NULL : No channel causing DMA interrupt
|
|
* ! NULL : Handle to a channel causing DMA interrupt
|
|
* @note
|
|
* dmacHw_clearInterrupt() must be called with a valid handle after calling this function
|
|
*/
|
|
/****************************************************************************/
|
|
dmacHw_HANDLE_t dmacHw_getInterruptSource(void);
|
|
|
|
/****************************************************************************/
|
|
/**
|
|
* @brief Sets channel specific user data
|
|
*
|
|
* This function associates user data to a specif DMA channel
|
|
*
|
|
*/
|
|
/****************************************************************************/
|
|
void dmacHw_setChannelUserData(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
|
|
void *userData /* [ IN ] User data */
|
|
);
|
|
|
|
/****************************************************************************/
|
|
/**
|
|
* @brief Gets channel specific user data
|
|
*
|
|
* This function returns user data specific to a DMA channel
|
|
*
|
|
* @return user data
|
|
*/
|
|
/****************************************************************************/
|
|
void *dmacHw_getChannelUserData(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */
|
|
);
|
|
|
|
/****************************************************************************/
|
|
/**
|
|
* @brief Displays channel specific registers and other control parameters
|
|
*
|
|
*
|
|
* @return void
|
|
*
|
|
* @note
|
|
* None
|
|
*/
|
|
/****************************************************************************/
|
|
void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
|
|
void *pDescriptor, /* [ IN ] Descriptor buffer */
|
|
int (*fpPrint) (const char *, ...) /* [ IN ] Print callback function */
|
|
);
|
|
|
|
/****************************************************************************/
|
|
/**
|
|
* @brief Provides DMA controller attributes
|
|
*
|
|
*
|
|
* @return DMA controller attributes
|
|
*
|
|
* @note
|
|
* None
|
|
*/
|
|
/****************************************************************************/
|
|
uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */
|
|
dmacHw_CONTROLLER_ATTRIB_e attr /* [ IN ] DMA Controler attribute of type dmacHw_CONTROLLER_ATTRIB_e */
|
|
);
|
|
|
|
#endif /* _DMACHW_H */
|