mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-10-31 12:39:23 +00:00
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
228 lines
5.1 KiB
C
228 lines
5.1 KiB
C
/*
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* linux/include/asm-arm/hardware/iomd.h
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*
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* Copyright (C) 1999 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This file contains information out the IOMD ASIC used in the
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* Acorn RiscPC and subsequently integrated into the CLPS7500 chips.
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*/
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#ifndef __ASMARM_HARDWARE_IOMD_H
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#define __ASMARM_HARDWARE_IOMD_H
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#include <linux/config.h>
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#ifndef __ASSEMBLY__
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/*
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* We use __raw_base variants here so that we give the compiler the
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* chance to keep IOC_BASE in a register.
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*/
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#define iomd_readb(off) __raw_readb(IOMD_BASE + (off))
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#define iomd_readl(off) __raw_readl(IOMD_BASE + (off))
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#define iomd_writeb(val,off) __raw_writeb(val, IOMD_BASE + (off))
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#define iomd_writel(val,off) __raw_writel(val, IOMD_BASE + (off))
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#endif
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#define IOMD_CONTROL (0x000)
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#define IOMD_KARTTX (0x004)
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#define IOMD_KARTRX (0x004)
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#define IOMD_KCTRL (0x008)
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#ifdef CONFIG_ARCH_CLPS7500
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#define IOMD_IOLINES (0x00C)
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#endif
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#define IOMD_IRQSTATA (0x010)
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#define IOMD_IRQREQA (0x014)
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#define IOMD_IRQCLRA (0x014)
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#define IOMD_IRQMASKA (0x018)
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#ifdef CONFIG_ARCH_CLPS7500
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#define IOMD_SUSMODE (0x01C)
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#endif
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#define IOMD_IRQSTATB (0x020)
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#define IOMD_IRQREQB (0x024)
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#define IOMD_IRQMASKB (0x028)
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#define IOMD_FIQSTAT (0x030)
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#define IOMD_FIQREQ (0x034)
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#define IOMD_FIQMASK (0x038)
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#ifdef CONFIG_ARCH_CLPS7500
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#define IOMD_CLKCTL (0x03C)
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#endif
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#define IOMD_T0CNTL (0x040)
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#define IOMD_T0LTCHL (0x040)
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#define IOMD_T0CNTH (0x044)
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#define IOMD_T0LTCHH (0x044)
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#define IOMD_T0GO (0x048)
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#define IOMD_T0LATCH (0x04c)
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#define IOMD_T1CNTL (0x050)
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#define IOMD_T1LTCHL (0x050)
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#define IOMD_T1CNTH (0x054)
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#define IOMD_T1LTCHH (0x054)
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#define IOMD_T1GO (0x058)
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#define IOMD_T1LATCH (0x05c)
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#ifdef CONFIG_ARCH_CLPS7500
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#define IOMD_IRQSTATC (0x060)
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#define IOMD_IRQREQC (0x064)
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#define IOMD_IRQMASKC (0x068)
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#define IOMD_VIDMUX (0x06c)
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#define IOMD_IRQSTATD (0x070)
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#define IOMD_IRQREQD (0x074)
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#define IOMD_IRQMASKD (0x078)
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#endif
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#define IOMD_ROMCR0 (0x080)
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#define IOMD_ROMCR1 (0x084)
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#ifdef CONFIG_ARCH_RPC
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#define IOMD_DRAMCR (0x088)
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#endif
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#define IOMD_REFCR (0x08C)
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#define IOMD_FSIZE (0x090)
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#define IOMD_ID0 (0x094)
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#define IOMD_ID1 (0x098)
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#define IOMD_VERSION (0x09C)
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#ifdef CONFIG_ARCH_RPC
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#define IOMD_MOUSEX (0x0A0)
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#define IOMD_MOUSEY (0x0A4)
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#endif
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#ifdef CONFIG_ARCH_CLPS7500
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#define IOMD_MSEDAT (0x0A8)
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#define IOMD_MSECTL (0x0Ac)
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#endif
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#ifdef CONFIG_ARCH_RPC
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#define IOMD_DMATCR (0x0C0)
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#endif
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#define IOMD_IOTCR (0x0C4)
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#define IOMD_ECTCR (0x0C8)
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#ifdef CONFIG_ARCH_RPC
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#define IOMD_DMAEXT (0x0CC)
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#endif
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#ifdef CONFIG_ARCH_CLPS7500
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#define IOMD_ASTCR (0x0CC)
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#define IOMD_DRAMCR (0x0D0)
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#define IOMD_SELFREF (0x0D4)
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#define IOMD_ATODICR (0x0E0)
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#define IOMD_ATODSR (0x0E4)
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#define IOMD_ATODCC (0x0E8)
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#define IOMD_ATODCNT1 (0x0EC)
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#define IOMD_ATODCNT2 (0x0F0)
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#define IOMD_ATODCNT3 (0x0F4)
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#define IOMD_ATODCNT4 (0x0F8)
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#endif
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#ifdef CONFIG_ARCH_RPC
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#define DMA_EXT_IO0 1
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#define DMA_EXT_IO1 2
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#define DMA_EXT_IO2 4
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#define DMA_EXT_IO3 8
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#define IOMD_IO0CURA (0x100)
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#define IOMD_IO0ENDA (0x104)
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#define IOMD_IO0CURB (0x108)
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#define IOMD_IO0ENDB (0x10C)
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#define IOMD_IO0CR (0x110)
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#define IOMD_IO0ST (0x114)
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#define IOMD_IO1CURA (0x120)
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#define IOMD_IO1ENDA (0x124)
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#define IOMD_IO1CURB (0x128)
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#define IOMD_IO1ENDB (0x12C)
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#define IOMD_IO1CR (0x130)
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#define IOMD_IO1ST (0x134)
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#define IOMD_IO2CURA (0x140)
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#define IOMD_IO2ENDA (0x144)
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#define IOMD_IO2CURB (0x148)
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#define IOMD_IO2ENDB (0x14C)
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#define IOMD_IO2CR (0x150)
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#define IOMD_IO2ST (0x154)
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#define IOMD_IO3CURA (0x160)
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#define IOMD_IO3ENDA (0x164)
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#define IOMD_IO3CURB (0x168)
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#define IOMD_IO3ENDB (0x16C)
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#define IOMD_IO3CR (0x170)
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#define IOMD_IO3ST (0x174)
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#endif
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#define IOMD_SD0CURA (0x180)
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#define IOMD_SD0ENDA (0x184)
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#define IOMD_SD0CURB (0x188)
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#define IOMD_SD0ENDB (0x18C)
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#define IOMD_SD0CR (0x190)
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#define IOMD_SD0ST (0x194)
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#ifdef CONFIG_ARCH_RPC
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#define IOMD_SD1CURA (0x1A0)
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#define IOMD_SD1ENDA (0x1A4)
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#define IOMD_SD1CURB (0x1A8)
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#define IOMD_SD1ENDB (0x1AC)
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#define IOMD_SD1CR (0x1B0)
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#define IOMD_SD1ST (0x1B4)
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#endif
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#define IOMD_CURSCUR (0x1C0)
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#define IOMD_CURSINIT (0x1C4)
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#define IOMD_VIDCUR (0x1D0)
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#define IOMD_VIDEND (0x1D4)
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#define IOMD_VIDSTART (0x1D8)
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#define IOMD_VIDINIT (0x1DC)
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#define IOMD_VIDCR (0x1E0)
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#define IOMD_DMASTAT (0x1F0)
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#define IOMD_DMAREQ (0x1F4)
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#define IOMD_DMAMASK (0x1F8)
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#define DMA_END_S (1 << 31)
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#define DMA_END_L (1 << 30)
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#define DMA_CR_C 0x80
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#define DMA_CR_D 0x40
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#define DMA_CR_E 0x20
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#define DMA_ST_OFL 4
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#define DMA_ST_INT 2
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#define DMA_ST_AB 1
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/*
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* DMA (MEMC) compatibility
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*/
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#define HALF_SAM vram_half_sam
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#define VDMA_ALIGNMENT (HALF_SAM * 2)
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#define VDMA_XFERSIZE (HALF_SAM)
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#define VDMA_INIT IOMD_VIDINIT
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#define VDMA_START IOMD_VIDSTART
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#define VDMA_END IOMD_VIDEND
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#ifndef __ASSEMBLY__
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extern unsigned int vram_half_sam;
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#define video_set_dma(start,end,offset) \
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do { \
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outl (SCREEN_START + start, VDMA_START); \
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outl (SCREEN_START + end - VDMA_XFERSIZE, VDMA_END); \
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if (offset >= end - VDMA_XFERSIZE) \
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offset |= 0x40000000; \
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outl (SCREEN_START + offset, VDMA_INIT); \
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} while (0)
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#endif
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#endif
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