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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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ec4d79255c
Scorpion-based SOCs from Qualcomm use a different interrupt controller 'sirc'. Signed-off-by: Gregory Bean <gbean@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org> Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
116 lines
4.8 KiB
C
116 lines
4.8 KiB
C
/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Code Aurora Forum, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef __ASM_ARCH_MSM_SIRC_H
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#define __ASM_ARCH_MSM_SIRC_H
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struct sirc_regs_t {
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void *int_enable;
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void *int_enable_clear;
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void *int_enable_set;
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void *int_type;
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void *int_polarity;
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void *int_clear;
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};
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struct sirc_cascade_regs {
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void *int_status;
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unsigned int cascade_irq;
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};
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void msm_init_sirc(void);
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void msm_sirc_enter_sleep(void);
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void msm_sirc_exit_sleep(void);
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#if defined(CONFIG_ARCH_MSM_SCORPION)
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#include <mach/msm_iomap.h>
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/*
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* Secondary interrupt controller interrupts
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*/
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#define FIRST_SIRC_IRQ (NR_MSM_IRQS + NR_GPIO_IRQS)
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#define INT_UART1 (FIRST_SIRC_IRQ + 0)
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#define INT_UART2 (FIRST_SIRC_IRQ + 1)
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#define INT_UART3 (FIRST_SIRC_IRQ + 2)
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#define INT_UART1_RX (FIRST_SIRC_IRQ + 3)
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#define INT_UART2_RX (FIRST_SIRC_IRQ + 4)
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#define INT_UART3_RX (FIRST_SIRC_IRQ + 5)
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#define INT_SPI_INPUT (FIRST_SIRC_IRQ + 6)
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#define INT_SPI_OUTPUT (FIRST_SIRC_IRQ + 7)
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#define INT_SPI_ERROR (FIRST_SIRC_IRQ + 8)
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#define INT_GPIO_GROUP1 (FIRST_SIRC_IRQ + 9)
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#define INT_GPIO_GROUP2 (FIRST_SIRC_IRQ + 10)
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#define INT_GPIO_GROUP1_SECURE (FIRST_SIRC_IRQ + 11)
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#define INT_GPIO_GROUP2_SECURE (FIRST_SIRC_IRQ + 12)
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#define INT_AVS_SVIC (FIRST_SIRC_IRQ + 13)
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#define INT_AVS_REQ_UP (FIRST_SIRC_IRQ + 14)
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#define INT_AVS_REQ_DOWN (FIRST_SIRC_IRQ + 15)
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#define INT_PBUS_ERR (FIRST_SIRC_IRQ + 16)
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#define INT_AXI_ERR (FIRST_SIRC_IRQ + 17)
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#define INT_SMI_ERR (FIRST_SIRC_IRQ + 18)
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#define INT_EBI1_ERR (FIRST_SIRC_IRQ + 19)
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#define INT_IMEM_ERR (FIRST_SIRC_IRQ + 20)
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#define INT_TEMP_SENSOR (FIRST_SIRC_IRQ + 21)
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#define INT_TV_ENC (FIRST_SIRC_IRQ + 22)
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#define INT_GRP2D (FIRST_SIRC_IRQ + 23)
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#define INT_GSBI_QUP (FIRST_SIRC_IRQ + 24)
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#define INT_SC_ACG (FIRST_SIRC_IRQ + 25)
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#define INT_WDT0 (FIRST_SIRC_IRQ + 26)
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#define INT_WDT1 (FIRST_SIRC_IRQ + 27)
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#if defined(CONFIG_MSM_SOC_REV_A)
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#define NR_SIRC_IRQS 28
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#define SIRC_MASK 0x0FFFFFFF
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#else
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#define NR_SIRC_IRQS 23
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#define SIRC_MASK 0x007FFFFF
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#endif
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#define LAST_SIRC_IRQ (FIRST_SIRC_IRQ + NR_SIRC_IRQS - 1)
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#define SPSS_SIRC_INT_SELECT (MSM_SIRC_BASE + 0x00)
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#define SPSS_SIRC_INT_ENABLE (MSM_SIRC_BASE + 0x04)
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#define SPSS_SIRC_INT_ENABLE_CLEAR (MSM_SIRC_BASE + 0x08)
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#define SPSS_SIRC_INT_ENABLE_SET (MSM_SIRC_BASE + 0x0C)
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#define SPSS_SIRC_INT_TYPE (MSM_SIRC_BASE + 0x10)
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#define SPSS_SIRC_INT_POLARITY (MSM_SIRC_BASE + 0x14)
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#define SPSS_SIRC_SECURITY (MSM_SIRC_BASE + 0x18)
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#define SPSS_SIRC_IRQ_STATUS (MSM_SIRC_BASE + 0x1C)
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#define SPSS_SIRC_IRQ1_STATUS (MSM_SIRC_BASE + 0x20)
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#define SPSS_SIRC_RAW_STATUS (MSM_SIRC_BASE + 0x24)
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#define SPSS_SIRC_INT_CLEAR (MSM_SIRC_BASE + 0x28)
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#define SPSS_SIRC_SOFT_INT (MSM_SIRC_BASE + 0x2C)
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#endif
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#endif
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