mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-10-31 14:30:50 +00:00
6fc5582580
In the process of merging Book3S_32 and 64 I somehow ended up having the alignment interrupt handler take last_inst, but the fetching code not fetching it. So we ended up with stale last_inst values. Let's just enable last_inst fetching for alignment interrupts too. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Avi Kivity <avi@redhat.com>
260 lines
6.8 KiB
ArmAsm
260 lines
6.8 KiB
ArmAsm
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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* Copyright SUSE Linux Products GmbH 2010
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*
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* Authors: Alexander Graf <agraf@suse.de>
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*/
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/* Real mode helpers */
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#if defined(CONFIG_PPC_BOOK3S_64)
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#define GET_SHADOW_VCPU(reg) \
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addi reg, r13, PACA_KVM_SVCPU
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#elif defined(CONFIG_PPC_BOOK3S_32)
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#define GET_SHADOW_VCPU(reg) \
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tophys(reg, r2); \
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lwz reg, (THREAD + THREAD_KVM_SVCPU)(reg); \
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tophys(reg, reg)
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#endif
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/* Disable for nested KVM */
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#define USE_QUICK_LAST_INST
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/* Get helper functions for subarch specific functionality */
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#if defined(CONFIG_PPC_BOOK3S_64)
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#include "book3s_64_slb.S"
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#elif defined(CONFIG_PPC_BOOK3S_32)
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#include "book3s_32_sr.S"
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#endif
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/******************************************************************************
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* *
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* Entry code *
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* *
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*****************************************************************************/
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.global kvmppc_handler_trampoline_enter
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kvmppc_handler_trampoline_enter:
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/* Required state:
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*
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* MSR = ~IR|DR
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* R13 = PACA
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* R1 = host R1
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* R2 = host R2
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* R10 = guest MSR
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* all other volatile GPRS = free
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* SVCPU[CR] = guest CR
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* SVCPU[XER] = guest XER
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* SVCPU[CTR] = guest CTR
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* SVCPU[LR] = guest LR
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*/
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/* r3 = shadow vcpu */
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GET_SHADOW_VCPU(r3)
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/* Move SRR0 and SRR1 into the respective regs */
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PPC_LL r9, SVCPU_PC(r3)
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mtsrr0 r9
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mtsrr1 r10
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/* Activate guest mode, so faults get handled by KVM */
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li r11, KVM_GUEST_MODE_GUEST
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stb r11, SVCPU_IN_GUEST(r3)
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/* Switch to guest segment. This is subarch specific. */
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LOAD_GUEST_SEGMENTS
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/* Enter guest */
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PPC_LL r4, (SVCPU_CTR)(r3)
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PPC_LL r5, (SVCPU_LR)(r3)
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lwz r6, (SVCPU_CR)(r3)
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lwz r7, (SVCPU_XER)(r3)
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mtctr r4
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mtlr r5
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mtcr r6
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mtxer r7
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PPC_LL r0, (SVCPU_R0)(r3)
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PPC_LL r1, (SVCPU_R1)(r3)
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PPC_LL r2, (SVCPU_R2)(r3)
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PPC_LL r4, (SVCPU_R4)(r3)
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PPC_LL r5, (SVCPU_R5)(r3)
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PPC_LL r6, (SVCPU_R6)(r3)
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PPC_LL r7, (SVCPU_R7)(r3)
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PPC_LL r8, (SVCPU_R8)(r3)
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PPC_LL r9, (SVCPU_R9)(r3)
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PPC_LL r10, (SVCPU_R10)(r3)
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PPC_LL r11, (SVCPU_R11)(r3)
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PPC_LL r12, (SVCPU_R12)(r3)
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PPC_LL r13, (SVCPU_R13)(r3)
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PPC_LL r3, (SVCPU_R3)(r3)
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RFI
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kvmppc_handler_trampoline_enter_end:
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/******************************************************************************
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* *
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* Exit code *
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* *
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*****************************************************************************/
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.global kvmppc_handler_trampoline_exit
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kvmppc_handler_trampoline_exit:
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/* Register usage at this point:
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*
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* SPRG_SCRATCH0 = guest R13
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* R12 = exit handler id
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* R13 = shadow vcpu - SHADOW_VCPU_OFF [=PACA on PPC64]
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* SVCPU.SCRATCH0 = guest R12
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* SVCPU.SCRATCH1 = guest CR
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*
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*/
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/* Save registers */
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PPC_STL r0, (SHADOW_VCPU_OFF + SVCPU_R0)(r13)
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PPC_STL r1, (SHADOW_VCPU_OFF + SVCPU_R1)(r13)
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PPC_STL r2, (SHADOW_VCPU_OFF + SVCPU_R2)(r13)
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PPC_STL r3, (SHADOW_VCPU_OFF + SVCPU_R3)(r13)
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PPC_STL r4, (SHADOW_VCPU_OFF + SVCPU_R4)(r13)
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PPC_STL r5, (SHADOW_VCPU_OFF + SVCPU_R5)(r13)
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PPC_STL r6, (SHADOW_VCPU_OFF + SVCPU_R6)(r13)
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PPC_STL r7, (SHADOW_VCPU_OFF + SVCPU_R7)(r13)
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PPC_STL r8, (SHADOW_VCPU_OFF + SVCPU_R8)(r13)
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PPC_STL r9, (SHADOW_VCPU_OFF + SVCPU_R9)(r13)
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PPC_STL r10, (SHADOW_VCPU_OFF + SVCPU_R10)(r13)
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PPC_STL r11, (SHADOW_VCPU_OFF + SVCPU_R11)(r13)
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/* Restore R1/R2 so we can handle faults */
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PPC_LL r1, (SHADOW_VCPU_OFF + SVCPU_HOST_R1)(r13)
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PPC_LL r2, (SHADOW_VCPU_OFF + SVCPU_HOST_R2)(r13)
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/* Save guest PC and MSR */
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mfsrr0 r3
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mfsrr1 r4
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PPC_STL r3, (SHADOW_VCPU_OFF + SVCPU_PC)(r13)
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PPC_STL r4, (SHADOW_VCPU_OFF + SVCPU_SHADOW_SRR1)(r13)
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/* Get scratch'ed off registers */
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mfspr r9, SPRN_SPRG_SCRATCH0
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PPC_LL r8, (SHADOW_VCPU_OFF + SVCPU_SCRATCH0)(r13)
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lwz r7, (SHADOW_VCPU_OFF + SVCPU_SCRATCH1)(r13)
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PPC_STL r9, (SHADOW_VCPU_OFF + SVCPU_R13)(r13)
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PPC_STL r8, (SHADOW_VCPU_OFF + SVCPU_R12)(r13)
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stw r7, (SHADOW_VCPU_OFF + SVCPU_CR)(r13)
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/* Save more register state */
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mfxer r5
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mfdar r6
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mfdsisr r7
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mfctr r8
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mflr r9
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stw r5, (SHADOW_VCPU_OFF + SVCPU_XER)(r13)
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PPC_STL r6, (SHADOW_VCPU_OFF + SVCPU_FAULT_DAR)(r13)
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stw r7, (SHADOW_VCPU_OFF + SVCPU_FAULT_DSISR)(r13)
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PPC_STL r8, (SHADOW_VCPU_OFF + SVCPU_CTR)(r13)
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PPC_STL r9, (SHADOW_VCPU_OFF + SVCPU_LR)(r13)
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/*
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* In order for us to easily get the last instruction,
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* we got the #vmexit at, we exploit the fact that the
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* virtual layout is still the same here, so we can just
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* ld from the guest's PC address
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*/
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/* We only load the last instruction when it's safe */
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cmpwi r12, BOOK3S_INTERRUPT_DATA_STORAGE
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beq ld_last_inst
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cmpwi r12, BOOK3S_INTERRUPT_PROGRAM
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beq ld_last_inst
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cmpwi r12, BOOK3S_INTERRUPT_ALIGNMENT
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beq- ld_last_inst
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b no_ld_last_inst
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ld_last_inst:
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/* Save off the guest instruction we're at */
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/* In case lwz faults */
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li r0, KVM_INST_FETCH_FAILED
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#ifdef USE_QUICK_LAST_INST
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/* Set guest mode to 'jump over instruction' so if lwz faults
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* we'll just continue at the next IP. */
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li r9, KVM_GUEST_MODE_SKIP
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stb r9, (SHADOW_VCPU_OFF + SVCPU_IN_GUEST)(r13)
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/* 1) enable paging for data */
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mfmsr r9
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ori r11, r9, MSR_DR /* Enable paging for data */
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mtmsr r11
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sync
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/* 2) fetch the instruction */
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lwz r0, 0(r3)
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/* 3) disable paging again */
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mtmsr r9
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sync
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#endif
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stw r0, (SHADOW_VCPU_OFF + SVCPU_LAST_INST)(r13)
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no_ld_last_inst:
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/* Unset guest mode */
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li r9, KVM_GUEST_MODE_NONE
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stb r9, (SHADOW_VCPU_OFF + SVCPU_IN_GUEST)(r13)
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/* Switch back to host MMU */
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LOAD_HOST_SEGMENTS
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/* Register usage at this point:
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*
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* R1 = host R1
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* R2 = host R2
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* R12 = exit handler id
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* R13 = shadow vcpu - SHADOW_VCPU_OFF [=PACA on PPC64]
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* SVCPU.* = guest *
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*
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*/
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/* RFI into the highmem handler */
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mfmsr r7
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ori r7, r7, MSR_IR|MSR_DR|MSR_RI|MSR_ME /* Enable paging */
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mtsrr1 r7
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/* Load highmem handler address */
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PPC_LL r8, (SHADOW_VCPU_OFF + SVCPU_VMHANDLER)(r13)
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mtsrr0 r8
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RFI
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kvmppc_handler_trampoline_exit_end:
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