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b8b572e101
from include/asm-powerpc. This is the result of a mkdir arch/powerpc/include/asm git mv include/asm-powerpc/* arch/powerpc/include/asm Followed by a few documentation/comment fixups and a couple of places where <asm-powepc/...> was being used explicitly. Of the latter only one was outside the arch code and it is a driver only built for powerpc. Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
68 lines
2.5 KiB
C
68 lines
2.5 KiB
C
#ifndef _ASM_POWERPC_HEATHROW_H
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#define _ASM_POWERPC_HEATHROW_H
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#ifdef __KERNEL__
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/*
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* heathrow.h: definitions for using the "Heathrow" I/O controller chip.
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*
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* Grabbed from Open Firmware definitions on a PowerBook G3 Series
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*
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* Copyright (C) 1997 Paul Mackerras.
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*/
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/* Front light color on Yikes/B&W G3. 32 bits */
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#define HEATHROW_FRONT_LIGHT 0x32 /* (set to 0 or 0xffffffff) */
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/* Brightness/contrast (gossamer iMac ?). 8 bits */
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#define HEATHROW_BRIGHTNESS_CNTL 0x32
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#define HEATHROW_CONTRAST_CNTL 0x33
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/* offset from ohare base for feature control register */
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#define HEATHROW_MBCR 0x34 /* Media bay control */
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#define HEATHROW_FCR 0x38 /* Feature control */
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#define HEATHROW_AUX_CNTL_REG 0x3c /* Aux control */
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/*
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* Bits in feature control register.
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* Bits postfixed with a _N are in inverse logic
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*/
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#define HRW_SCC_TRANS_EN_N 0x00000001 /* Also controls modem power */
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#define HRW_BAY_POWER_N 0x00000002
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#define HRW_BAY_PCI_ENABLE 0x00000004
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#define HRW_BAY_IDE_ENABLE 0x00000008
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#define HRW_BAY_FLOPPY_ENABLE 0x00000010
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#define HRW_IDE0_ENABLE 0x00000020
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#define HRW_IDE0_RESET_N 0x00000040
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#define HRW_BAY_DEV_MASK 0x0000001c
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#define HRW_BAY_RESET_N 0x00000080
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#define HRW_IOBUS_ENABLE 0x00000100 /* Internal IDE ? */
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#define HRW_SCC_ENABLE 0x00000200
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#define HRW_MESH_ENABLE 0x00000400
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#define HRW_SWIM_ENABLE 0x00000800
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#define HRW_SOUND_POWER_N 0x00001000
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#define HRW_SOUND_CLK_ENABLE 0x00002000
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#define HRW_SCCA_IO 0x00004000
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#define HRW_SCCB_IO 0x00008000
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#define HRW_PORT_OR_DESK_VIA_N 0x00010000 /* This one is 0 on PowerBook */
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#define HRW_PWM_MON_ID_N 0x00020000 /* ??? (0) */
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#define HRW_HOOK_MB_CNT_N 0x00040000 /* ??? (0) */
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#define HRW_SWIM_CLONE_FLOPPY 0x00080000 /* ??? (0) */
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#define HRW_AUD_RUN22 0x00100000 /* ??? (1) */
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#define HRW_SCSI_LINK_MODE 0x00200000 /* Read ??? (1) */
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#define HRW_ARB_BYPASS 0x00400000 /* Disable internal PCI arbitrer */
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#define HRW_IDE1_RESET_N 0x00800000 /* Media bay */
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#define HRW_SLOW_SCC_PCLK 0x01000000 /* ??? (0) */
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#define HRW_RESET_SCC 0x02000000
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#define HRW_MFDC_CELL_ENABLE 0x04000000 /* ??? (0) */
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#define HRW_USE_MFDC 0x08000000 /* ??? (0) */
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#define HRW_BMAC_IO_ENABLE 0x60000000 /* two bits, not documented in OF */
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#define HRW_BMAC_RESET 0x80000000 /* not documented in OF */
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/* We OR those features at boot on desktop G3s */
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#define HRW_DEFAULTS (HRW_SCCA_IO | HRW_SCCB_IO | HRW_SCC_ENABLE)
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/* Looks like Heathrow has some sort of GPIOs as well... */
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#define HRW_GPIO_MODEM_RESET 0x6d
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_HEATHROW_H */
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