mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-10-31 14:06:03 +00:00
f9f3d31318
Signed-off-by: Gregory Bean <gbean@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org> Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
366 lines
11 KiB
C
366 lines
11 KiB
C
/*
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* Copyright (C) 2007 Google, Inc.
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* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/ptrace.h>
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#include <linux/timer.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/cacheflush.h>
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#include <mach/hardware.h>
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#include <mach/msm_iomap.h>
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#include "smd_private.h"
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enum {
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IRQ_DEBUG_SLEEP_INT_TRIGGER = 1U << 0,
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IRQ_DEBUG_SLEEP_INT = 1U << 1,
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IRQ_DEBUG_SLEEP_ABORT = 1U << 2,
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IRQ_DEBUG_SLEEP = 1U << 3,
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IRQ_DEBUG_SLEEP_REQUEST = 1U << 4,
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};
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static int msm_irq_debug_mask;
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module_param_named(debug_mask, msm_irq_debug_mask, int,
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S_IRUGO | S_IWUSR | S_IWGRP);
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#define VIC_REG(off) (MSM_VIC_BASE + (off))
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#define VIC_INT_TO_REG_ADDR(base, irq) (base + (irq / 32) * 4)
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#define VIC_INT_TO_REG_INDEX(irq) ((irq >> 5) & 3)
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#define VIC_INT_SELECT0 VIC_REG(0x0000) /* 1: FIQ, 0: IRQ */
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#define VIC_INT_SELECT1 VIC_REG(0x0004) /* 1: FIQ, 0: IRQ */
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#define VIC_INT_SELECT2 VIC_REG(0x0008) /* 1: FIQ, 0: IRQ */
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#define VIC_INT_SELECT3 VIC_REG(0x000C) /* 1: FIQ, 0: IRQ */
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#define VIC_INT_EN0 VIC_REG(0x0010)
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#define VIC_INT_EN1 VIC_REG(0x0014)
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#define VIC_INT_EN2 VIC_REG(0x0018)
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#define VIC_INT_EN3 VIC_REG(0x001C)
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#define VIC_INT_ENCLEAR0 VIC_REG(0x0020)
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#define VIC_INT_ENCLEAR1 VIC_REG(0x0024)
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#define VIC_INT_ENCLEAR2 VIC_REG(0x0028)
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#define VIC_INT_ENCLEAR3 VIC_REG(0x002C)
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#define VIC_INT_ENSET0 VIC_REG(0x0030)
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#define VIC_INT_ENSET1 VIC_REG(0x0034)
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#define VIC_INT_ENSET2 VIC_REG(0x0038)
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#define VIC_INT_ENSET3 VIC_REG(0x003C)
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#define VIC_INT_TYPE0 VIC_REG(0x0040) /* 1: EDGE, 0: LEVEL */
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#define VIC_INT_TYPE1 VIC_REG(0x0044) /* 1: EDGE, 0: LEVEL */
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#define VIC_INT_TYPE2 VIC_REG(0x0048) /* 1: EDGE, 0: LEVEL */
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#define VIC_INT_TYPE3 VIC_REG(0x004C) /* 1: EDGE, 0: LEVEL */
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#define VIC_INT_POLARITY0 VIC_REG(0x0050) /* 1: NEG, 0: POS */
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#define VIC_INT_POLARITY1 VIC_REG(0x0054) /* 1: NEG, 0: POS */
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#define VIC_INT_POLARITY2 VIC_REG(0x0058) /* 1: NEG, 0: POS */
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#define VIC_INT_POLARITY3 VIC_REG(0x005C) /* 1: NEG, 0: POS */
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#define VIC_NO_PEND_VAL VIC_REG(0x0060)
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#if defined(CONFIG_ARCH_MSM_SCORPION)
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#define VIC_NO_PEND_VAL_FIQ VIC_REG(0x0064)
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#define VIC_INT_MASTEREN VIC_REG(0x0068) /* 1: IRQ, 2: FIQ */
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#define VIC_CONFIG VIC_REG(0x006C) /* 1: USE SC VIC */
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#else
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#define VIC_INT_MASTEREN VIC_REG(0x0064) /* 1: IRQ, 2: FIQ */
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#define VIC_PROTECTION VIC_REG(0x006C) /* 1: ENABLE */
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#define VIC_CONFIG VIC_REG(0x0068) /* 1: USE ARM1136 VIC */
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#endif
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#define VIC_IRQ_STATUS0 VIC_REG(0x0080)
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#define VIC_IRQ_STATUS1 VIC_REG(0x0084)
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#define VIC_IRQ_STATUS2 VIC_REG(0x0088)
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#define VIC_IRQ_STATUS3 VIC_REG(0x008C)
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#define VIC_FIQ_STATUS0 VIC_REG(0x0090)
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#define VIC_FIQ_STATUS1 VIC_REG(0x0094)
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#define VIC_FIQ_STATUS2 VIC_REG(0x0098)
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#define VIC_FIQ_STATUS3 VIC_REG(0x009C)
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#define VIC_RAW_STATUS0 VIC_REG(0x00A0)
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#define VIC_RAW_STATUS1 VIC_REG(0x00A4)
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#define VIC_RAW_STATUS2 VIC_REG(0x00A8)
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#define VIC_RAW_STATUS3 VIC_REG(0x00AC)
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#define VIC_INT_CLEAR0 VIC_REG(0x00B0)
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#define VIC_INT_CLEAR1 VIC_REG(0x00B4)
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#define VIC_INT_CLEAR2 VIC_REG(0x00B8)
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#define VIC_INT_CLEAR3 VIC_REG(0x00BC)
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#define VIC_SOFTINT0 VIC_REG(0x00C0)
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#define VIC_SOFTINT1 VIC_REG(0x00C4)
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#define VIC_SOFTINT2 VIC_REG(0x00C8)
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#define VIC_SOFTINT3 VIC_REG(0x00CC)
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#define VIC_IRQ_VEC_RD VIC_REG(0x00D0) /* pending int # */
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#define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4) /* pending vector addr */
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#define VIC_IRQ_VEC_WR VIC_REG(0x00D8)
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#if defined(CONFIG_ARCH_MSM_SCORPION)
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#define VIC_FIQ_VEC_RD VIC_REG(0x00DC)
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#define VIC_FIQ_VEC_PEND_RD VIC_REG(0x00E0)
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#define VIC_FIQ_VEC_WR VIC_REG(0x00E4)
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#define VIC_IRQ_IN_SERVICE VIC_REG(0x00E8)
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#define VIC_IRQ_IN_STACK VIC_REG(0x00EC)
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#define VIC_FIQ_IN_SERVICE VIC_REG(0x00F0)
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#define VIC_FIQ_IN_STACK VIC_REG(0x00F4)
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#define VIC_TEST_BUS_SEL VIC_REG(0x00F8)
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#define VIC_IRQ_CTRL_CONFIG VIC_REG(0x00FC)
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#else
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#define VIC_IRQ_IN_SERVICE VIC_REG(0x00E0)
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#define VIC_IRQ_IN_STACK VIC_REG(0x00E4)
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#define VIC_TEST_BUS_SEL VIC_REG(0x00E8)
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#endif
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#define VIC_VECTPRIORITY(n) VIC_REG(0x0200+((n) * 4))
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#define VIC_VECTADDR(n) VIC_REG(0x0400+((n) * 4))
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#if defined(CONFIG_ARCH_MSM7X30)
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#define VIC_NUM_REGS 4
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#else
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#define VIC_NUM_REGS 2
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#endif
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#if VIC_NUM_REGS == 2
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#define DPRINT_REGS(base_reg, format, ...) \
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printk(KERN_INFO format " %x %x\n", ##__VA_ARGS__, \
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readl(base_reg ## 0), readl(base_reg ## 1))
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#define DPRINT_ARRAY(array, format, ...) \
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printk(KERN_INFO format " %x %x\n", ##__VA_ARGS__, \
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array[0], array[1])
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#elif VIC_NUM_REGS == 4
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#define DPRINT_REGS(base_reg, format, ...) \
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printk(KERN_INFO format " %x %x %x %x\n", ##__VA_ARGS__, \
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readl(base_reg ## 0), readl(base_reg ## 1), \
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readl(base_reg ## 2), readl(base_reg ## 3))
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#define DPRINT_ARRAY(array, format, ...) \
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printk(KERN_INFO format " %x %x %x %x\n", ##__VA_ARGS__, \
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array[0], array[1], \
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array[2], array[3])
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#else
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#error "VIC_NUM_REGS set to illegal value"
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#endif
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static uint32_t msm_irq_smsm_wake_enable[2];
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static struct {
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uint32_t int_en[2];
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uint32_t int_type;
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uint32_t int_polarity;
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uint32_t int_select;
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} msm_irq_shadow_reg[VIC_NUM_REGS];
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static uint32_t msm_irq_idle_disable[VIC_NUM_REGS];
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#define SMSM_FAKE_IRQ (0xff)
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static uint8_t msm_irq_to_smsm[NR_IRQS] = {
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[INT_MDDI_EXT] = 1,
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[INT_MDDI_PRI] = 2,
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[INT_MDDI_CLIENT] = 3,
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[INT_USB_OTG] = 4,
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[INT_PWB_I2C] = 5,
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[INT_SDC1_0] = 6,
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[INT_SDC1_1] = 7,
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[INT_SDC2_0] = 8,
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[INT_SDC2_1] = 9,
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[INT_ADSP_A9_A11] = 10,
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[INT_UART1] = 11,
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[INT_UART2] = 12,
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[INT_UART3] = 13,
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[INT_UART1_RX] = 14,
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[INT_UART2_RX] = 15,
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[INT_UART3_RX] = 16,
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[INT_UART1DM_IRQ] = 17,
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[INT_UART1DM_RX] = 18,
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[INT_KEYSENSE] = 19,
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#if !defined(CONFIG_ARCH_MSM7X30)
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[INT_AD_HSSD] = 20,
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#endif
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[INT_NAND_WR_ER_DONE] = 21,
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[INT_NAND_OP_DONE] = 22,
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[INT_TCHSCRN1] = 23,
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[INT_TCHSCRN2] = 24,
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[INT_TCHSCRN_SSBI] = 25,
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[INT_USB_HS] = 26,
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[INT_UART2DM_RX] = 27,
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[INT_UART2DM_IRQ] = 28,
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[INT_SDC4_1] = 29,
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[INT_SDC4_0] = 30,
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[INT_SDC3_1] = 31,
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[INT_SDC3_0] = 32,
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/* fake wakeup interrupts */
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[INT_GPIO_GROUP1] = SMSM_FAKE_IRQ,
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[INT_GPIO_GROUP2] = SMSM_FAKE_IRQ,
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[INT_A9_M2A_0] = SMSM_FAKE_IRQ,
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[INT_A9_M2A_1] = SMSM_FAKE_IRQ,
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[INT_A9_M2A_5] = SMSM_FAKE_IRQ,
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[INT_GP_TIMER_EXP] = SMSM_FAKE_IRQ,
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[INT_DEBUG_TIMER_EXP] = SMSM_FAKE_IRQ,
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[INT_ADSP_A11] = SMSM_FAKE_IRQ,
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#ifdef CONFIG_ARCH_QSD8X50
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[INT_SIRC_0] = SMSM_FAKE_IRQ,
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[INT_SIRC_1] = SMSM_FAKE_IRQ,
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#endif
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};
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static inline void msm_irq_write_all_regs(void __iomem *base, unsigned int val)
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{
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int i;
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for (i = 0; i < VIC_NUM_REGS; i++)
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writel(val, base + (i * 4));
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}
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static void msm_irq_ack(unsigned int irq)
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{
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void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_CLEAR0, irq);
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irq = 1 << (irq & 31);
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writel(irq, reg);
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}
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static void msm_irq_mask(unsigned int irq)
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{
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void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENCLEAR0, irq);
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unsigned index = VIC_INT_TO_REG_INDEX(irq);
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uint32_t mask = 1UL << (irq & 31);
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int smsm_irq = msm_irq_to_smsm[irq];
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msm_irq_shadow_reg[index].int_en[0] &= ~mask;
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writel(mask, reg);
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if (smsm_irq == 0)
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msm_irq_idle_disable[index] &= ~mask;
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else {
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mask = 1UL << (smsm_irq - 1);
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msm_irq_smsm_wake_enable[0] &= ~mask;
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}
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}
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static void msm_irq_unmask(unsigned int irq)
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{
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void __iomem *reg = VIC_INT_TO_REG_ADDR(VIC_INT_ENSET0, irq);
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unsigned index = VIC_INT_TO_REG_INDEX(irq);
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uint32_t mask = 1UL << (irq & 31);
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int smsm_irq = msm_irq_to_smsm[irq];
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msm_irq_shadow_reg[index].int_en[0] |= mask;
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writel(mask, reg);
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if (smsm_irq == 0)
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msm_irq_idle_disable[index] |= mask;
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else {
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mask = 1UL << (smsm_irq - 1);
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msm_irq_smsm_wake_enable[0] |= mask;
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}
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}
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static int msm_irq_set_wake(unsigned int irq, unsigned int on)
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{
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unsigned index = VIC_INT_TO_REG_INDEX(irq);
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uint32_t mask = 1UL << (irq & 31);
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int smsm_irq = msm_irq_to_smsm[irq];
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if (smsm_irq == 0) {
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printk(KERN_ERR "msm_irq_set_wake: bad wakeup irq %d\n", irq);
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return -EINVAL;
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}
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if (on)
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msm_irq_shadow_reg[index].int_en[1] |= mask;
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else
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msm_irq_shadow_reg[index].int_en[1] &= ~mask;
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if (smsm_irq == SMSM_FAKE_IRQ)
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return 0;
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mask = 1UL << (smsm_irq - 1);
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if (on)
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msm_irq_smsm_wake_enable[1] |= mask;
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else
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msm_irq_smsm_wake_enable[1] &= ~mask;
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return 0;
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}
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static int msm_irq_set_type(unsigned int irq, unsigned int flow_type)
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{
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void __iomem *treg = VIC_INT_TO_REG_ADDR(VIC_INT_TYPE0, irq);
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void __iomem *preg = VIC_INT_TO_REG_ADDR(VIC_INT_POLARITY0, irq);
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unsigned index = VIC_INT_TO_REG_INDEX(irq);
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int b = 1 << (irq & 31);
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uint32_t polarity;
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uint32_t type;
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polarity = msm_irq_shadow_reg[index].int_polarity;
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if (flow_type & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_LOW))
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polarity |= b;
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if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH))
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polarity &= ~b;
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writel(polarity, preg);
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msm_irq_shadow_reg[index].int_polarity = polarity;
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type = msm_irq_shadow_reg[index].int_type;
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if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
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type |= b;
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irq_desc[irq].handle_irq = handle_edge_irq;
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}
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if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
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type &= ~b;
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irq_desc[irq].handle_irq = handle_level_irq;
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}
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writel(type, treg);
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msm_irq_shadow_reg[index].int_type = type;
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return 0;
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}
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static struct irq_chip msm_irq_chip = {
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.name = "msm",
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.disable = msm_irq_mask,
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.ack = msm_irq_ack,
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.mask = msm_irq_mask,
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.unmask = msm_irq_unmask,
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.set_wake = msm_irq_set_wake,
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.set_type = msm_irq_set_type,
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};
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void __init msm_init_irq(void)
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{
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unsigned n;
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/* select level interrupts */
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msm_irq_write_all_regs(VIC_INT_TYPE0, 0);
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/* select highlevel interrupts */
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msm_irq_write_all_regs(VIC_INT_POLARITY0, 0);
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/* select IRQ for all INTs */
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msm_irq_write_all_regs(VIC_INT_SELECT0, 0);
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/* disable all INTs */
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msm_irq_write_all_regs(VIC_INT_EN0, 0);
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/* don't use vic */
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writel(0, VIC_CONFIG);
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/* enable interrupt controller */
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writel(3, VIC_INT_MASTEREN);
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for (n = 0; n < NR_MSM_IRQS; n++) {
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set_irq_chip(n, &msm_irq_chip);
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set_irq_handler(n, handle_level_irq);
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set_irq_flags(n, IRQF_VALID);
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}
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}
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