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2783cc265c
Install a gpiolib driver supporting the on-chip gpios for single-core MSMs in the 7x00 family, including 7x00A, 7x25, 7x27, 7x30, 8x50, and 8x50a. As part of the ongoing effort to converge on a common code base, this driver is based on the Google-Android msmgpio driver, whose authors include Brian Swetland and Arve Hjønnevåg. Cc: Arve Hjønnevåg <arve@android.com> Cc: H Hartley Sweeten <hartleys@visionengravers.com> Cc: Ryan Mallon <ryan@bluewatersys.com> Cc: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Gregory Bean <gbean@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
279 lines
12 KiB
C
279 lines
12 KiB
C
/* arch/arm/mach-msm/gpio_hw.h
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*
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* Copyright (C) 2007 Google, Inc.
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* Author: Brian Swetland <swetland@google.com>
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* Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __ARCH_ARM_MACH_MSM_GPIO_HW_H
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#define __ARCH_ARM_MACH_MSM_GPIO_HW_H
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#include <mach/msm_iomap.h>
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/* see 80-VA736-2 Rev C pp 695-751
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**
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** These are actually the *shadow* gpio registers, since the
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** real ones (which allow full access) are only available to the
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** ARM9 side of the world.
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**
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** Since the _BASE need to be page-aligned when we're mapping them
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** to virtual addresses, adjust for the additional offset in these
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** macros.
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*/
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#if defined(CONFIG_ARCH_MSM7X30)
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#define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + (off))
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#define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0x400 + (off))
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#else
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#define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + 0x800 + (off))
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#define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off))
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#endif
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#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X25) ||\
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defined(CONFIG_ARCH_MSM7X27)
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/* output value */
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#define MSM_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */
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#define MSM_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 42-16 */
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#define MSM_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-43 */
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#define MSM_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */
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#define MSM_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 106-95 */
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#define MSM_GPIO_OUT_5 MSM_GPIO1_REG(0x50) /* gpio 107-121 */
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/* same pin map as above, output enable */
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#define MSM_GPIO_OE_0 MSM_GPIO1_REG(0x10)
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#define MSM_GPIO_OE_1 MSM_GPIO2_REG(0x08)
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#define MSM_GPIO_OE_2 MSM_GPIO1_REG(0x14)
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#define MSM_GPIO_OE_3 MSM_GPIO1_REG(0x18)
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#define MSM_GPIO_OE_4 MSM_GPIO1_REG(0x1C)
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#define MSM_GPIO_OE_5 MSM_GPIO1_REG(0x54)
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/* same pin map as above, input read */
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#define MSM_GPIO_IN_0 MSM_GPIO1_REG(0x34)
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#define MSM_GPIO_IN_1 MSM_GPIO2_REG(0x20)
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#define MSM_GPIO_IN_2 MSM_GPIO1_REG(0x38)
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#define MSM_GPIO_IN_3 MSM_GPIO1_REG(0x3C)
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#define MSM_GPIO_IN_4 MSM_GPIO1_REG(0x40)
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#define MSM_GPIO_IN_5 MSM_GPIO1_REG(0x44)
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/* same pin map as above, 1=edge 0=level interrup */
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#define MSM_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x60)
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#define MSM_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50)
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#define MSM_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x64)
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#define MSM_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x68)
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#define MSM_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x6C)
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#define MSM_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0xC0)
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/* same pin map as above, 1=positive 0=negative */
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#define MSM_GPIO_INT_POS_0 MSM_GPIO1_REG(0x70)
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#define MSM_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58)
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#define MSM_GPIO_INT_POS_2 MSM_GPIO1_REG(0x74)
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#define MSM_GPIO_INT_POS_3 MSM_GPIO1_REG(0x78)
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#define MSM_GPIO_INT_POS_4 MSM_GPIO1_REG(0x7C)
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#define MSM_GPIO_INT_POS_5 MSM_GPIO1_REG(0xBC)
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/* same pin map as above, interrupt enable */
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#define MSM_GPIO_INT_EN_0 MSM_GPIO1_REG(0x80)
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#define MSM_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60)
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#define MSM_GPIO_INT_EN_2 MSM_GPIO1_REG(0x84)
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#define MSM_GPIO_INT_EN_3 MSM_GPIO1_REG(0x88)
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#define MSM_GPIO_INT_EN_4 MSM_GPIO1_REG(0x8C)
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#define MSM_GPIO_INT_EN_5 MSM_GPIO1_REG(0xB8)
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/* same pin map as above, write 1 to clear interrupt */
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#define MSM_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0x90)
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#define MSM_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68)
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#define MSM_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0x94)
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#define MSM_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0x98)
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#define MSM_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0x9C)
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#define MSM_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xB4)
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/* same pin map as above, 1=interrupt pending */
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#define MSM_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xA0)
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#define MSM_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70)
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#define MSM_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xA4)
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#define MSM_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xA8)
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#define MSM_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xAC)
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#define MSM_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0xB0)
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#endif
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#if defined(CONFIG_ARCH_QSD8X50)
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/* output value */
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#define MSM_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */
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#define MSM_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 42-16 */
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#define MSM_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-43 */
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#define MSM_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */
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#define MSM_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 103-95 */
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#define MSM_GPIO_OUT_5 MSM_GPIO1_REG(0x10) /* gpio 121-104 */
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#define MSM_GPIO_OUT_6 MSM_GPIO1_REG(0x14) /* gpio 152-122 */
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#define MSM_GPIO_OUT_7 MSM_GPIO1_REG(0x18) /* gpio 164-153 */
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/* same pin map as above, output enable */
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#define MSM_GPIO_OE_0 MSM_GPIO1_REG(0x20)
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#define MSM_GPIO_OE_1 MSM_GPIO2_REG(0x08)
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#define MSM_GPIO_OE_2 MSM_GPIO1_REG(0x24)
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#define MSM_GPIO_OE_3 MSM_GPIO1_REG(0x28)
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#define MSM_GPIO_OE_4 MSM_GPIO1_REG(0x2C)
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#define MSM_GPIO_OE_5 MSM_GPIO1_REG(0x30)
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#define MSM_GPIO_OE_6 MSM_GPIO1_REG(0x34)
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#define MSM_GPIO_OE_7 MSM_GPIO1_REG(0x38)
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/* same pin map as above, input read */
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#define MSM_GPIO_IN_0 MSM_GPIO1_REG(0x50)
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#define MSM_GPIO_IN_1 MSM_GPIO2_REG(0x20)
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#define MSM_GPIO_IN_2 MSM_GPIO1_REG(0x54)
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#define MSM_GPIO_IN_3 MSM_GPIO1_REG(0x58)
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#define MSM_GPIO_IN_4 MSM_GPIO1_REG(0x5C)
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#define MSM_GPIO_IN_5 MSM_GPIO1_REG(0x60)
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#define MSM_GPIO_IN_6 MSM_GPIO1_REG(0x64)
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#define MSM_GPIO_IN_7 MSM_GPIO1_REG(0x68)
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/* same pin map as above, 1=edge 0=level interrup */
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#define MSM_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x70)
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#define MSM_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50)
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#define MSM_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x74)
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#define MSM_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x78)
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#define MSM_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x7C)
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#define MSM_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0x80)
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#define MSM_GPIO_INT_EDGE_6 MSM_GPIO1_REG(0x84)
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#define MSM_GPIO_INT_EDGE_7 MSM_GPIO1_REG(0x88)
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/* same pin map as above, 1=positive 0=negative */
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#define MSM_GPIO_INT_POS_0 MSM_GPIO1_REG(0x90)
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#define MSM_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58)
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#define MSM_GPIO_INT_POS_2 MSM_GPIO1_REG(0x94)
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#define MSM_GPIO_INT_POS_3 MSM_GPIO1_REG(0x98)
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#define MSM_GPIO_INT_POS_4 MSM_GPIO1_REG(0x9C)
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#define MSM_GPIO_INT_POS_5 MSM_GPIO1_REG(0xA0)
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#define MSM_GPIO_INT_POS_6 MSM_GPIO1_REG(0xA4)
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#define MSM_GPIO_INT_POS_7 MSM_GPIO1_REG(0xA8)
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/* same pin map as above, interrupt enable */
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#define MSM_GPIO_INT_EN_0 MSM_GPIO1_REG(0xB0)
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#define MSM_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60)
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#define MSM_GPIO_INT_EN_2 MSM_GPIO1_REG(0xB4)
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#define MSM_GPIO_INT_EN_3 MSM_GPIO1_REG(0xB8)
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#define MSM_GPIO_INT_EN_4 MSM_GPIO1_REG(0xBC)
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#define MSM_GPIO_INT_EN_5 MSM_GPIO1_REG(0xC0)
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#define MSM_GPIO_INT_EN_6 MSM_GPIO1_REG(0xC4)
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#define MSM_GPIO_INT_EN_7 MSM_GPIO1_REG(0xC8)
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/* same pin map as above, write 1 to clear interrupt */
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#define MSM_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0xD0)
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#define MSM_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68)
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#define MSM_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0xD4)
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#define MSM_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0xD8)
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#define MSM_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0xDC)
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#define MSM_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xE0)
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#define MSM_GPIO_INT_CLEAR_6 MSM_GPIO1_REG(0xE4)
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#define MSM_GPIO_INT_CLEAR_7 MSM_GPIO1_REG(0xE8)
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/* same pin map as above, 1=interrupt pending */
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#define MSM_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xF0)
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#define MSM_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70)
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#define MSM_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xF4)
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#define MSM_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xF8)
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#define MSM_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xFC)
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#define MSM_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0x100)
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#define MSM_GPIO_INT_STATUS_6 MSM_GPIO1_REG(0x104)
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#define MSM_GPIO_INT_STATUS_7 MSM_GPIO1_REG(0x108)
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#endif
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#if defined(CONFIG_ARCH_MSM7X30)
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/* output value */
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#define MSM_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */
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#define MSM_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 43-16 */
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#define MSM_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-44 */
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#define MSM_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */
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#define MSM_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 106-95 */
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#define MSM_GPIO_OUT_5 MSM_GPIO1_REG(0x50) /* gpio 133-107 */
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#define MSM_GPIO_OUT_6 MSM_GPIO1_REG(0xC4) /* gpio 150-134 */
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#define MSM_GPIO_OUT_7 MSM_GPIO1_REG(0x214) /* gpio 181-151 */
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/* same pin map as above, output enable */
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#define MSM_GPIO_OE_0 MSM_GPIO1_REG(0x10)
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#define MSM_GPIO_OE_1 MSM_GPIO2_REG(0x08)
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#define MSM_GPIO_OE_2 MSM_GPIO1_REG(0x14)
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#define MSM_GPIO_OE_3 MSM_GPIO1_REG(0x18)
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#define MSM_GPIO_OE_4 MSM_GPIO1_REG(0x1C)
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#define MSM_GPIO_OE_5 MSM_GPIO1_REG(0x54)
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#define MSM_GPIO_OE_6 MSM_GPIO1_REG(0xC8)
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#define MSM_GPIO_OE_7 MSM_GPIO1_REG(0x218)
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/* same pin map as above, input read */
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#define MSM_GPIO_IN_0 MSM_GPIO1_REG(0x34)
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#define MSM_GPIO_IN_1 MSM_GPIO2_REG(0x20)
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#define MSM_GPIO_IN_2 MSM_GPIO1_REG(0x38)
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#define MSM_GPIO_IN_3 MSM_GPIO1_REG(0x3C)
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#define MSM_GPIO_IN_4 MSM_GPIO1_REG(0x40)
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#define MSM_GPIO_IN_5 MSM_GPIO1_REG(0x44)
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#define MSM_GPIO_IN_6 MSM_GPIO1_REG(0xCC)
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#define MSM_GPIO_IN_7 MSM_GPIO1_REG(0x21C)
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/* same pin map as above, 1=edge 0=level interrup */
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#define MSM_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x60)
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#define MSM_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50)
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#define MSM_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x64)
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#define MSM_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x68)
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#define MSM_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x6C)
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#define MSM_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0xC0)
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#define MSM_GPIO_INT_EDGE_6 MSM_GPIO1_REG(0xD0)
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#define MSM_GPIO_INT_EDGE_7 MSM_GPIO1_REG(0x240)
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/* same pin map as above, 1=positive 0=negative */
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#define MSM_GPIO_INT_POS_0 MSM_GPIO1_REG(0x70)
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#define MSM_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58)
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#define MSM_GPIO_INT_POS_2 MSM_GPIO1_REG(0x74)
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#define MSM_GPIO_INT_POS_3 MSM_GPIO1_REG(0x78)
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#define MSM_GPIO_INT_POS_4 MSM_GPIO1_REG(0x7C)
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#define MSM_GPIO_INT_POS_5 MSM_GPIO1_REG(0xBC)
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#define MSM_GPIO_INT_POS_6 MSM_GPIO1_REG(0xD4)
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#define MSM_GPIO_INT_POS_7 MSM_GPIO1_REG(0x228)
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/* same pin map as above, interrupt enable */
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#define MSM_GPIO_INT_EN_0 MSM_GPIO1_REG(0x80)
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#define MSM_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60)
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#define MSM_GPIO_INT_EN_2 MSM_GPIO1_REG(0x84)
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#define MSM_GPIO_INT_EN_3 MSM_GPIO1_REG(0x88)
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#define MSM_GPIO_INT_EN_4 MSM_GPIO1_REG(0x8C)
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#define MSM_GPIO_INT_EN_5 MSM_GPIO1_REG(0xB8)
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#define MSM_GPIO_INT_EN_6 MSM_GPIO1_REG(0xD8)
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#define MSM_GPIO_INT_EN_7 MSM_GPIO1_REG(0x22C)
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/* same pin map as above, write 1 to clear interrupt */
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#define MSM_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0x90)
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#define MSM_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68)
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#define MSM_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0x94)
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#define MSM_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0x98)
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#define MSM_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0x9C)
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#define MSM_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xB4)
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#define MSM_GPIO_INT_CLEAR_6 MSM_GPIO1_REG(0xDC)
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#define MSM_GPIO_INT_CLEAR_7 MSM_GPIO1_REG(0x230)
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/* same pin map as above, 1=interrupt pending */
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#define MSM_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xA0)
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#define MSM_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70)
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#define MSM_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xA4)
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#define MSM_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xA8)
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#define MSM_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xAC)
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#define MSM_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0xB0)
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#define MSM_GPIO_INT_STATUS_6 MSM_GPIO1_REG(0xE0)
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#define MSM_GPIO_INT_STATUS_7 MSM_GPIO1_REG(0x234)
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#endif
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#endif
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