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e360adbe29
Provide a mechanism that allows running code in IRQ context. It is most useful for NMI code that needs to interact with the rest of the system -- like wakeup a task to drain buffers. Perf currently has such a mechanism, so extract that and provide it as a generic feature, independent of perf so that others may also benefit. The IRQ context callback is generated through self-IPIs where possible, or on architectures like powerpc the decrementer (the built-in timer facility) is set to generate an interrupt immediately. Architectures that don't have anything like this get to do with a callback from the timer tick. These architectures can call irq_work_run() at the tail of any IRQ handlers that might enqueue such work (like the perf IRQ handler) to avoid undue latencies in processing the work. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Acked-by: Kyle McMartin <kyle@mcmartin.ca> Acked-by: Martin Schwidefsky <schwidefsky@de.ibm.com> [ various fixes ] Signed-off-by: Huang Ying <ying.huang@intel.com> LKML-Reference: <1287036094.7768.291.camel@yhuang-dev> Signed-off-by: Ingo Molnar <mingo@elte.hu>
37 lines
891 B
C
37 lines
891 B
C
/*
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* linux/arch/arm/include/asm/perf_event.h
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*
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* Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef __ARM_PERF_EVENT_H__
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#define __ARM_PERF_EVENT_H__
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/* ARM performance counters start from 1 (in the cp15 accesses) so use the
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* same indexes here for consistency. */
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#define PERF_EVENT_INDEX_OFFSET 1
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/* ARM perf PMU IDs for use by internal perf clients. */
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enum arm_perf_pmu_ids {
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ARM_PERF_PMU_ID_XSCALE1 = 0,
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ARM_PERF_PMU_ID_XSCALE2,
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ARM_PERF_PMU_ID_V6,
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ARM_PERF_PMU_ID_V6MP,
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ARM_PERF_PMU_ID_CA8,
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ARM_PERF_PMU_ID_CA9,
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ARM_NUM_PMU_IDS,
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};
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extern enum arm_perf_pmu_ids
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armpmu_get_pmu_id(void);
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extern int
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armpmu_get_max_events(void);
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#endif /* __ARM_PERF_EVENT_H__ */
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