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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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864232fa1a
For debuggers to take advantage of the hw-breakpoint framework in the kernel, it is necessary to expose the API calls via a ptrace interface. This patch exposes the hardware breakpoints framework as a collection of virtual registers, accesible using PTRACE_SETHBPREGS and PTRACE_GETHBPREGS requests. The breakpoints are stored in the debug_info struct of the running thread. Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: S. Karthikeyan <informkarthik@gmail.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
134 lines
3.3 KiB
C
134 lines
3.3 KiB
C
#ifndef _ARM_HW_BREAKPOINT_H
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#define _ARM_HW_BREAKPOINT_H
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#ifdef __KERNEL__
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struct task_struct;
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#ifdef CONFIG_HAVE_HW_BREAKPOINT
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struct arch_hw_breakpoint_ctrl {
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u32 __reserved : 9,
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mismatch : 1,
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: 9,
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len : 8,
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type : 2,
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privilege : 2,
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enabled : 1;
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};
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struct arch_hw_breakpoint {
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u32 address;
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u32 trigger;
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struct perf_event *suspended_wp;
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struct arch_hw_breakpoint_ctrl ctrl;
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};
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static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl)
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{
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return (ctrl.mismatch << 22) | (ctrl.len << 5) | (ctrl.type << 3) |
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(ctrl.privilege << 1) | ctrl.enabled;
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}
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static inline void decode_ctrl_reg(u32 reg,
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struct arch_hw_breakpoint_ctrl *ctrl)
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{
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ctrl->enabled = reg & 0x1;
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reg >>= 1;
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ctrl->privilege = reg & 0x3;
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reg >>= 2;
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ctrl->type = reg & 0x3;
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reg >>= 2;
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ctrl->len = reg & 0xff;
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reg >>= 17;
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ctrl->mismatch = reg & 0x1;
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}
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/* Debug architecture numbers. */
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#define ARM_DEBUG_ARCH_RESERVED 0 /* In case of ptrace ABI updates. */
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#define ARM_DEBUG_ARCH_V6 1
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#define ARM_DEBUG_ARCH_V6_1 2
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#define ARM_DEBUG_ARCH_V7_ECP14 3
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#define ARM_DEBUG_ARCH_V7_MM 4
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/* Breakpoint */
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#define ARM_BREAKPOINT_EXECUTE 0
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/* Watchpoints */
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#define ARM_BREAKPOINT_LOAD 1
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#define ARM_BREAKPOINT_STORE 2
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/* Privilege Levels */
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#define ARM_BREAKPOINT_PRIV 1
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#define ARM_BREAKPOINT_USER 2
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/* Lengths */
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#define ARM_BREAKPOINT_LEN_1 0x1
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#define ARM_BREAKPOINT_LEN_2 0x3
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#define ARM_BREAKPOINT_LEN_4 0xf
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#define ARM_BREAKPOINT_LEN_8 0xff
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/* Limits */
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#define ARM_MAX_BRP 16
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#define ARM_MAX_WRP 16
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#define ARM_MAX_HBP_SLOTS (ARM_MAX_BRP + ARM_MAX_WRP)
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/* DSCR method of entry bits. */
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#define ARM_DSCR_MOE(x) ((x >> 2) & 0xf)
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#define ARM_ENTRY_BREAKPOINT 0x1
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#define ARM_ENTRY_ASYNC_WATCHPOINT 0x2
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#define ARM_ENTRY_SYNC_WATCHPOINT 0xa
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/* DSCR monitor/halting bits. */
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#define ARM_DSCR_HDBGEN (1 << 14)
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#define ARM_DSCR_MDBGEN (1 << 15)
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/* opcode2 numbers for the co-processor instructions. */
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#define ARM_OP2_BVR 4
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#define ARM_OP2_BCR 5
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#define ARM_OP2_WVR 6
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#define ARM_OP2_WCR 7
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/* Base register numbers for the debug registers. */
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#define ARM_BASE_BVR 64
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#define ARM_BASE_BCR 80
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#define ARM_BASE_WVR 96
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#define ARM_BASE_WCR 112
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/* Accessor macros for the debug registers. */
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#define ARM_DBG_READ(M, OP2, VAL) do {\
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asm volatile("mrc p14, 0, %0, c0," #M ", " #OP2 : "=r" (VAL));\
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} while (0)
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#define ARM_DBG_WRITE(M, OP2, VAL) do {\
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asm volatile("mcr p14, 0, %0, c0," #M ", " #OP2 : : "r" (VAL));\
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} while (0)
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struct notifier_block;
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struct perf_event;
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struct pmu;
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extern struct pmu perf_ops_bp;
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extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
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int *gen_len, int *gen_type);
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extern int arch_check_bp_in_kernelspace(struct perf_event *bp);
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extern int arch_validate_hwbkpt_settings(struct perf_event *bp);
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extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
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unsigned long val, void *data);
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extern u8 arch_get_debug_arch(void);
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extern u8 arch_get_max_wp_len(void);
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extern void clear_ptrace_hw_breakpoint(struct task_struct *tsk);
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int arch_install_hw_breakpoint(struct perf_event *bp);
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void arch_uninstall_hw_breakpoint(struct perf_event *bp);
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void hw_breakpoint_pmu_read(struct perf_event *bp);
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int hw_breakpoint_slots(int type);
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#else
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static inline void clear_ptrace_hw_breakpoint(struct task_struct *tsk) {}
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#endif /* CONFIG_HAVE_HW_BREAKPOINT */
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#endif /* __KERNEL__ */
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#endif /* _ARM_HW_BREAKPOINT_H */
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