mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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e404f91ed2
* git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile: arch/tile: convert a BUG_ON to BUILD_BUG_ON arch/tile: make ptrace() work properly for TILE-Gx COMPAT mode arch/tile: support new info op generated by compiler arch/tile: minor whitespace/naming changes for string support files arch/tile: enable single-step support for TILE-Gx arch/tile: parameterize system PLs to support KVM port arch/tile: add Tilera's <arch/sim.h> header as an open-source header arch/tile: Bomb C99 comments to C89 comments in tile's <arch/sim_def.h> arch/tile: prevent corrupt top frame from causing backtracer runaway arch/tile: various top-level Makefile cleanups arch/tile: change lower bound on syscall error return to -4095 arch/tile: properly export __mb_incoherent for modules arch/tile: provide a definition of MAP_STACK kmemleak: add TILE to the list of supported architectures. char: hvc: check for error case arch/tile: Add a warning if we try to allocate too much vmalloc memory. arch/tile: update some comments to clarify register usage. arch/tile: use better "punctuation" for VMSPLIT_3_5G and friends arch/tile: Use <asm-generic/syscalls.h> tile: replace some BUG_ON checks with BUILD_BUG_ON checks
269 lines
8.9 KiB
C
269 lines
8.9 KiB
C
/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#ifndef _ASM_TILE_IRQFLAGS_H
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#define _ASM_TILE_IRQFLAGS_H
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#include <arch/interrupts.h>
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#include <arch/chip.h>
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/*
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* The set of interrupts we want to allow when interrupts are nominally
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* disabled. The remainder are effectively "NMI" interrupts from
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* the point of view of the generic Linux code. Note that synchronous
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* interrupts (aka "non-queued") are not blocked by the mask in any case.
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*/
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#if CHIP_HAS_AUX_PERF_COUNTERS()
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#define LINUX_MASKABLE_INTERRUPTS \
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(~(INT_MASK(INT_PERF_COUNT) | INT_MASK(INT_AUX_PERF_COUNT)))
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#else
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#define LINUX_MASKABLE_INTERRUPTS \
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(~(INT_MASK(INT_PERF_COUNT)))
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#endif
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#ifndef __ASSEMBLY__
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/* NOTE: we can't include <linux/percpu.h> due to #include dependencies. */
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#include <asm/percpu.h>
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#include <arch/spr_def.h>
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/* Set and clear kernel interrupt masks. */
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#if CHIP_HAS_SPLIT_INTR_MASK()
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#if INT_PERF_COUNT < 32 || INT_AUX_PERF_COUNT < 32 || INT_MEM_ERROR >= 32
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# error Fix assumptions about which word various interrupts are in
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#endif
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#define interrupt_mask_set(n) do { \
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int __n = (n); \
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int __mask = 1 << (__n & 0x1f); \
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if (__n < 32) \
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__insn_mtspr(SPR_INTERRUPT_MASK_SET_K_0, __mask); \
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else \
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__insn_mtspr(SPR_INTERRUPT_MASK_SET_K_1, __mask); \
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} while (0)
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#define interrupt_mask_reset(n) do { \
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int __n = (n); \
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int __mask = 1 << (__n & 0x1f); \
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if (__n < 32) \
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__insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_0, __mask); \
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else \
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__insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_1, __mask); \
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} while (0)
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#define interrupt_mask_check(n) ({ \
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int __n = (n); \
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(((__n < 32) ? \
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__insn_mfspr(SPR_INTERRUPT_MASK_K_0) : \
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__insn_mfspr(SPR_INTERRUPT_MASK_K_1)) \
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>> (__n & 0x1f)) & 1; \
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})
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#define interrupt_mask_set_mask(mask) do { \
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unsigned long long __m = (mask); \
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__insn_mtspr(SPR_INTERRUPT_MASK_SET_K_0, (unsigned long)(__m)); \
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__insn_mtspr(SPR_INTERRUPT_MASK_SET_K_1, (unsigned long)(__m>>32)); \
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} while (0)
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#define interrupt_mask_reset_mask(mask) do { \
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unsigned long long __m = (mask); \
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__insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_0, (unsigned long)(__m)); \
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__insn_mtspr(SPR_INTERRUPT_MASK_RESET_K_1, (unsigned long)(__m>>32)); \
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} while (0)
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#else
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#define interrupt_mask_set(n) \
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__insn_mtspr(SPR_INTERRUPT_MASK_SET_K, (1UL << (n)))
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#define interrupt_mask_reset(n) \
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__insn_mtspr(SPR_INTERRUPT_MASK_RESET_K, (1UL << (n)))
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#define interrupt_mask_check(n) \
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((__insn_mfspr(SPR_INTERRUPT_MASK_K) >> (n)) & 1)
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#define interrupt_mask_set_mask(mask) \
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__insn_mtspr(SPR_INTERRUPT_MASK_SET_K, (mask))
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#define interrupt_mask_reset_mask(mask) \
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__insn_mtspr(SPR_INTERRUPT_MASK_RESET_K, (mask))
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#endif
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/*
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* The set of interrupts we want active if irqs are enabled.
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* Note that in particular, the tile timer interrupt comes and goes
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* from this set, since we have no other way to turn off the timer.
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* Likewise, INTCTRL_K is removed and re-added during device
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* interrupts, as is the the hardwall UDN_FIREWALL interrupt.
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* We use a low bit (MEM_ERROR) as our sentinel value and make sure it
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* is always claimed as an "active interrupt" so we can query that bit
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* to know our current state.
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*/
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DECLARE_PER_CPU(unsigned long long, interrupts_enabled_mask);
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#define INITIAL_INTERRUPTS_ENABLED INT_MASK(INT_MEM_ERROR)
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/* Disable interrupts. */
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#define arch_local_irq_disable() \
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interrupt_mask_set_mask(LINUX_MASKABLE_INTERRUPTS)
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/* Disable all interrupts, including NMIs. */
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#define arch_local_irq_disable_all() \
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interrupt_mask_set_mask(-1UL)
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/* Re-enable all maskable interrupts. */
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#define arch_local_irq_enable() \
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interrupt_mask_reset_mask(__get_cpu_var(interrupts_enabled_mask))
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/* Disable or enable interrupts based on flag argument. */
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#define arch_local_irq_restore(disabled) do { \
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if (disabled) \
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arch_local_irq_disable(); \
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else \
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arch_local_irq_enable(); \
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} while (0)
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/* Return true if "flags" argument means interrupts are disabled. */
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#define arch_irqs_disabled_flags(flags) ((flags) != 0)
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/* Return true if interrupts are currently disabled. */
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#define arch_irqs_disabled() interrupt_mask_check(INT_MEM_ERROR)
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/* Save whether interrupts are currently disabled. */
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#define arch_local_save_flags() arch_irqs_disabled()
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/* Save whether interrupts are currently disabled, then disable them. */
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#define arch_local_irq_save() ({ \
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unsigned long __flags = arch_local_save_flags(); \
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arch_local_irq_disable(); \
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__flags; })
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/* Prevent the given interrupt from being enabled next time we enable irqs. */
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#define arch_local_irq_mask(interrupt) \
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(__get_cpu_var(interrupts_enabled_mask) &= ~INT_MASK(interrupt))
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/* Prevent the given interrupt from being enabled immediately. */
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#define arch_local_irq_mask_now(interrupt) do { \
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arch_local_irq_mask(interrupt); \
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interrupt_mask_set(interrupt); \
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} while (0)
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/* Allow the given interrupt to be enabled next time we enable irqs. */
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#define arch_local_irq_unmask(interrupt) \
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(__get_cpu_var(interrupts_enabled_mask) |= INT_MASK(interrupt))
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/* Allow the given interrupt to be enabled immediately, if !irqs_disabled. */
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#define arch_local_irq_unmask_now(interrupt) do { \
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arch_local_irq_unmask(interrupt); \
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if (!irqs_disabled()) \
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interrupt_mask_reset(interrupt); \
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} while (0)
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#else /* __ASSEMBLY__ */
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/* We provide a somewhat more restricted set for assembly. */
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#ifdef __tilegx__
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#if INT_MEM_ERROR != 0
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# error Fix IRQ_DISABLED() macro
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#endif
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/* Return 0 or 1 to indicate whether interrupts are currently disabled. */
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#define IRQS_DISABLED(tmp) \
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mfspr tmp, SPR_INTERRUPT_MASK_K; \
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andi tmp, tmp, 1
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/* Load up a pointer to &interrupts_enabled_mask. */
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#define GET_INTERRUPTS_ENABLED_MASK_PTR(reg) \
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moveli reg, hw2_last(interrupts_enabled_mask); \
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shl16insli reg, reg, hw1(interrupts_enabled_mask); \
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shl16insli reg, reg, hw0(interrupts_enabled_mask); \
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add reg, reg, tp
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/* Disable interrupts. */
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#define IRQ_DISABLE(tmp0, tmp1) \
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moveli tmp0, hw2_last(LINUX_MASKABLE_INTERRUPTS); \
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shl16insli tmp0, tmp0, hw1(LINUX_MASKABLE_INTERRUPTS); \
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shl16insli tmp0, tmp0, hw0(LINUX_MASKABLE_INTERRUPTS); \
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mtspr SPR_INTERRUPT_MASK_SET_K, tmp0
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/* Disable ALL synchronous interrupts (used by NMI entry). */
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#define IRQ_DISABLE_ALL(tmp) \
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movei tmp, -1; \
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mtspr SPR_INTERRUPT_MASK_SET_K, tmp
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/* Enable interrupts. */
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#define IRQ_ENABLE(tmp0, tmp1) \
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GET_INTERRUPTS_ENABLED_MASK_PTR(tmp0); \
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ld tmp0, tmp0; \
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mtspr SPR_INTERRUPT_MASK_RESET_K, tmp0
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#else /* !__tilegx__ */
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/*
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* Return 0 or 1 to indicate whether interrupts are currently disabled.
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* Note that it's important that we use a bit from the "low" mask word,
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* since when we are enabling, that is the word we write first, so if we
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* are interrupted after only writing half of the mask, the interrupt
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* handler will correctly observe that we have interrupts enabled, and
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* will enable interrupts itself on return from the interrupt handler
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* (making the original code's write of the "high" mask word idempotent).
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*/
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#define IRQS_DISABLED(tmp) \
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mfspr tmp, SPR_INTERRUPT_MASK_K_0; \
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shri tmp, tmp, INT_MEM_ERROR; \
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andi tmp, tmp, 1
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/* Load up a pointer to &interrupts_enabled_mask. */
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#define GET_INTERRUPTS_ENABLED_MASK_PTR(reg) \
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moveli reg, lo16(interrupts_enabled_mask); \
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auli reg, reg, ha16(interrupts_enabled_mask); \
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add reg, reg, tp
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/* Disable interrupts. */
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#define IRQ_DISABLE(tmp0, tmp1) \
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{ \
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movei tmp0, -1; \
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moveli tmp1, lo16(LINUX_MASKABLE_INTERRUPTS) \
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}; \
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{ \
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mtspr SPR_INTERRUPT_MASK_SET_K_0, tmp0; \
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auli tmp1, tmp1, ha16(LINUX_MASKABLE_INTERRUPTS) \
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}; \
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mtspr SPR_INTERRUPT_MASK_SET_K_1, tmp1
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/* Disable ALL synchronous interrupts (used by NMI entry). */
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#define IRQ_DISABLE_ALL(tmp) \
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movei tmp, -1; \
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mtspr SPR_INTERRUPT_MASK_SET_K_0, tmp; \
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mtspr SPR_INTERRUPT_MASK_SET_K_1, tmp
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/* Enable interrupts. */
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#define IRQ_ENABLE(tmp0, tmp1) \
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GET_INTERRUPTS_ENABLED_MASK_PTR(tmp0); \
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{ \
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lw tmp0, tmp0; \
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addi tmp1, tmp0, 4 \
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}; \
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lw tmp1, tmp1; \
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mtspr SPR_INTERRUPT_MASK_RESET_K_0, tmp0; \
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mtspr SPR_INTERRUPT_MASK_RESET_K_1, tmp1
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#endif
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/*
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* Do the CPU's IRQ-state tracing from assembly code. We call a
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* C function, but almost everywhere we do, we don't mind clobbering
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* all the caller-saved registers.
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*/
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#ifdef CONFIG_TRACE_IRQFLAGS
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# define TRACE_IRQS_ON jal trace_hardirqs_on
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# define TRACE_IRQS_OFF jal trace_hardirqs_off
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#else
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# define TRACE_IRQS_ON
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# define TRACE_IRQS_OFF
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_TILE_IRQFLAGS_H */
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