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	 9d56dd3b08
			
		
	
	
		9d56dd3b08
		
	
	
	
	
		
			
			The old ctrl in/out routines are non-portable and unsuitable for cross-platform use. While drivers/sh has already been sanitized, there is still quite a lot of code that is not. This converts the arch/sh/ bits over, which permits us to flag the routines as deprecated whilst still building with -Werror for the architecture code, and to ensure that future users are not added. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
		
			
				
	
	
		
			86 lines
		
	
	
		
			1.9 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			86 lines
		
	
	
		
			1.9 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * arch/sh/kernel/cpu/sh2a/clock-sh7206.c
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|  *
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|  * SH7206 support for the clock framework
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|  *
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|  *  Copyright (C) 2006  Yoshinori Sato
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|  *
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|  * Based on clock-sh4.c
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|  *  Copyright (C) 2005  Paul Mundt
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|  *
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|  * This file is subject to the terms and conditions of the GNU General Public
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|  * License.  See the file "COPYING" in the main directory of this archive
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|  * for more details.
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|  */
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| #include <linux/init.h>
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| #include <linux/kernel.h>
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| #include <asm/clock.h>
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| #include <asm/freq.h>
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| #include <asm/io.h>
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| 
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| static const int pll1rate[]={1,2,3,4,6,8};
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| static const int pfc_divisors[]={1,2,3,4,6,8,12};
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| #define ifc_divisors pfc_divisors
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| 
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| #if (CONFIG_SH_CLK_MD == 2)
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| #define PLL2 (4)
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| #elif (CONFIG_SH_CLK_MD == 6)
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| #define PLL2 (2)
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| #elif (CONFIG_SH_CLK_MD == 7)
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| #define PLL2 (1)
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| #else
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| #error "Illigal Clock Mode!"
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| #endif
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| 
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| static void master_clk_init(struct clk *clk)
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| {
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| 	clk->rate *= PLL2 * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
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| }
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| 
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| static struct clk_ops sh7206_master_clk_ops = {
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| 	.init		= master_clk_init,
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| };
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| 
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| static unsigned long module_clk_recalc(struct clk *clk)
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| {
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| 	int idx = (__raw_readw(FREQCR) & 0x0007);
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| 	return clk->parent->rate / pfc_divisors[idx];
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| }
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| 
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| static struct clk_ops sh7206_module_clk_ops = {
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| 	.recalc		= module_clk_recalc,
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| };
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| 
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| static unsigned long bus_clk_recalc(struct clk *clk)
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| {
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| 	return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
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| }
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| 
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| static struct clk_ops sh7206_bus_clk_ops = {
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| 	.recalc		= bus_clk_recalc,
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| };
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| 
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| static unsigned long cpu_clk_recalc(struct clk *clk)
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| {
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| 	int idx = (__raw_readw(FREQCR) & 0x0007);
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| 	return clk->parent->rate / ifc_divisors[idx];
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| }
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| 
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| static struct clk_ops sh7206_cpu_clk_ops = {
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| 	.recalc		= cpu_clk_recalc,
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| };
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| 
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| static struct clk_ops *sh7206_clk_ops[] = {
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| 	&sh7206_master_clk_ops,
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| 	&sh7206_module_clk_ops,
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| 	&sh7206_bus_clk_ops,
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| 	&sh7206_cpu_clk_ops,
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| };
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| 
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| void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
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| {
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| 	if (idx < ARRAY_SIZE(sh7206_clk_ops))
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| 		*ops = sh7206_clk_ops[idx];
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| }
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| 
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