mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-10-31 06:18:54 +00:00
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
335 lines
5.5 KiB
ArmAsm
335 lines
5.5 KiB
ArmAsm
/*
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* fp_cond.S
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*
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* Copyright Roman Zippel, 1997. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, and the entire permission notice in its entirety,
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* including the disclaimer of warranties.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote
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* products derived from this software without specific prior
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* written permission.
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*
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* ALTERNATIVELY, this product may be distributed under the terms of
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* the GNU General Public License, in which case the provisions of the GPL are
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* required INSTEAD OF the above restrictions. (This clause is
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* necessary due to a potential bad interaction between the GPL and
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* the restrictions contained in a BSD-style copyright.)
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fp_emu.h"
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#include "fp_decode.h"
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.globl fp_fscc, fp_fbccw, fp_fbccl
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#ifdef FPU_EMU_DEBUG
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fp_fnop:
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printf PDECODE,"fnop\n"
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jra fp_end
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#else
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#define fp_fnop fp_end
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#endif
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fp_fbccw:
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tst.w %d2
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jeq fp_fnop
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printf PDECODE,"fbccw "
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fp_get_pc %a0
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lea (-2,%a0,%d2.w),%a0
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jra 1f
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fp_fbccl:
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printf PDECODE,"fbccl "
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fp_get_pc %a0
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move.l %d2,%d0
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swap %d0
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fp_get_instr_word %d0,fp_err_ua1
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lea (-2,%a0,%d0.l),%a0
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1: printf PDECODE,"%x",1,%a0
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move.l %d2,%d0
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swap %d0
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jsr fp_compute_cond
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tst.l %d0
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jeq 1f
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fp_put_pc %a0,1
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1: printf PDECODE,"\n"
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jra fp_end
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fp_fdbcc:
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printf PDECODE,"fdbcc "
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fp_get_pc %a1 | calculate new pc
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fp_get_instr_word %d0,fp_err_ua1
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add.w %d0,%a1
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fp_decode_addr_reg
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printf PDECODE,"d%d,%x\n",2,%d0,%a1
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swap %d1 | test condition in %d1
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tst.w %d1
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jne 2f
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move.l %d0,%d1
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jsr fp_get_data_reg
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subq.w #1,%d0
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jcs 1f
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fp_put_pc %a1,1
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1: jsr fp_put_data_reg
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2: jra fp_end
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| set flags for decode macros for fs<cc>
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do_fscc=1
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do_no_pc_mode=1
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fp_fscc:
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printf PDECODE,"fscc "
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move.l %d2,%d0
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jsr fp_compute_cond
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move.w %d0,%d1
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swap %d1
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| decode addressing mode
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fp_decode_addr_mode
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.long fp_data, fp_fdbcc
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.long fp_indirect, fp_postinc
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.long fp_predecr, fp_disp16
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.long fp_extmode0, fp_extmode1
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| addressing mode: data register direct
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fp_data:
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fp_mode_data_direct
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move.w %d0,%d1 | save register nr
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jsr fp_get_data_reg
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swap %d1
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move.b %d1,%d0
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swap %d1
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jsr fp_put_data_reg
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printf PDECODE,"\n"
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jra fp_end
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fp_indirect:
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fp_mode_addr_indirect
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jra fp_do_scc
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fp_postinc:
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fp_mode_addr_indirect_postinc
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jra fp_do_scc
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fp_predecr:
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fp_mode_addr_indirect_predec
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jra fp_do_scc
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fp_disp16:
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fp_mode_addr_indirect_disp16
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jra fp_do_scc
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fp_extmode0:
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fp_mode_addr_indirect_extmode0
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jra fp_do_scc
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fp_extmode1:
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bfextu %d2{#13,#3},%d0
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jmp ([0f:w,%pc,%d0*4])
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.align 4
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0:
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.long fp_absolute_short, fp_absolute_long
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.long fp_ill, fp_ill | NOTE: jump here to ftrap.x
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.long fp_ill, fp_ill
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.long fp_ill, fp_ill
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fp_absolute_short:
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fp_mode_abs_short
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jra fp_do_scc
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fp_absolute_long:
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fp_mode_abs_long
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| jra fp_do_scc
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fp_do_scc:
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swap %d1
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putuser.b %d1,(%a0),fp_err_ua1,%a0
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printf PDECODE,"\n"
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jra fp_end
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#define tst_NAN btst #24,%d1
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#define tst_Z btst #26,%d1
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#define tst_N btst #27,%d1
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fp_compute_cond:
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move.l (FPD_FPSR,FPDATA),%d1
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btst #4,%d0
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jeq 1f
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tst_NAN
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jeq 1f
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bset #15,%d1
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bset #7,%d1
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move.l %d1,(FPD_FPSR,FPDATA)
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1: and.w #0xf,%d0
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jmp ([0f:w,%pc,%d0.w*4])
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.align 4
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0:
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.long fp_f , fp_eq , fp_ogt, fp_oge
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.long fp_olt, fp_ole, fp_ogl, fp_or
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.long fp_un , fp_ueq, fp_ugt, fp_uge
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.long fp_ult, fp_ule, fp_ne , fp_t
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fp_f:
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moveq #0,%d0
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rts
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fp_eq:
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moveq #0,%d0
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tst_Z
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jeq 1f
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moveq #-1,%d0
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1: rts
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fp_ogt:
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moveq #0,%d0
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tst_NAN
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jne 1f
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tst_Z
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jne 1f
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tst_N
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jne 1f
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moveq #-1,%d0
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1: rts
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fp_oge:
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moveq #-1,%d0
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tst_Z
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jne 2f
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tst_NAN
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jne 1f
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tst_N
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jeq 2f
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1: moveq #0,%d0
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2: rts
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fp_olt:
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moveq #0,%d0
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tst_NAN
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jne 1f
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tst_Z
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jne 1f
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tst_N
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jeq 1f
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moveq #-1,%d0
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1: rts
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fp_ole:
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moveq #-1,%d0
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tst_Z
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jne 2f
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tst_NAN
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jne 1f
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tst_N
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jne 2f
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1: moveq #0,%d0
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2: rts
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fp_ogl:
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moveq #0,%d0
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tst_NAN
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jne 1f
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tst_Z
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jne 1f
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moveq #-1,%d0
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1: rts
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fp_or:
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moveq #0,%d0
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tst_NAN
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jne 1f
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moveq #-1,%d0
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1: rts
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fp_un:
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moveq #0,%d0
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tst_NAN
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jeq 1f
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moveq #-1,%d0
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rts
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fp_ueq:
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moveq #-1,%d0
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tst_NAN
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jne 1f
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tst_Z
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jne 1f
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moveq #0,%d0
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1: rts
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fp_ugt:
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moveq #-1,%d0
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tst_NAN
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jne 2f
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tst_N
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jne 1f
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tst_Z
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jeq 2f
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1: moveq #0,%d0
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2: rts
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fp_uge:
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moveq #-1,%d0
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tst_NAN
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jne 1f
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tst_Z
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jne 1f
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tst_N
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jeq 1f
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moveq #0,%d0
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1: rts
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fp_ult:
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moveq #-1,%d0
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tst_NAN
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jne 2f
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tst_Z
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jne 1f
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tst_N
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jne 2f
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1: moveq #0,%d0
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2: rts
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fp_ule:
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moveq #-1,%d0
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tst_NAN
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jne 1f
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tst_Z
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jne 1f
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tst_N
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jne 1f
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moveq #0,%d0
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1: rts
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fp_ne:
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moveq #0,%d0
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tst_Z
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jne 1f
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moveq #-1,%d0
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1: rts
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fp_t:
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moveq #-1,%d0
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rts
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